Verilog-Operators:

Arithmetic Operators:
 Unary Operators

 Perform operation with only one operand.

 It shows the Operand is Negative or Positive.

 Unary operators are ” – “ and “+”

 Binary Operators

 Perform operation with two operands

Operator Symbol Operation Performed Number of Operands

+ Addition two
- Subtraction two
* Multiply two
/ Divide two
% Modulus two
** Power(Exponential) two
Logical Operators:

Operator Symbol Operation Number of Operands

! Logical Negation One
&& Logical AND Two
|| Logical OR Two
Bitwise Operators:

 It can perform bit by bit operation.

 It takes each bit from one operand and perform the operation with the corresponding
bit in other operand.

Operator Symbol Operation Number of

Operands
& Bitwise AND Two
| Bitwise OR Two
~ Bitwise Negation One
^ Bitwise XOR Two
~^ or ^~ Bitwise XNOR Two
Equality Operators:
Operator Symbol Operation Number of Operands
== Logical Equality Two
!= Logical Inequality Two
=== Case Equality Two
!== Case Inequality Two

Result of both Logical & Case Equality Operators are logic-1 or logic-0.

Difference b/w logical & Case equality operators are

 Logical Equality operators will not consider “X” and “Z” components. It results “X”, when
the above components involved during operation.

 Case Equality operators will consider “X” and “Z” components during operation.
Relational Operators:

Greater than (>)

 Less than (<)

 Greater than or Equal (>=)

 Less than or Equal (<=)

Note:

Result either logic-1 or logic-0.

 Result is “x”, when operands contains “x”

Reduction Operators:
 Only One Operand.

 Performs Bitwise operation on only one operand and the Result is one bit
1’b1 or 1’b0.

 Reduction operators are

and (&)
 or (|)
 nand (~&)
 nor (~|)
xor (^)
 xnor (~^ , ^~)
Shift Operators:
 Regular Shift Operators:

Regular Shift operators can shift the operand to the Left or Right number of bits.

After Shift operation, Vacant bit positions are filled with zero.

Arithmetic Shift Operators:

Arithmetic Shift operators can shift the operand to the Left or Right number of
bits.

 After shift operation, Vacant bit positions are filled with a value which can be
determined by considering context of the expression.
Concatenation Operator:

In any computation, Operands must be sized.

Concatenation Operator used to resize the operand.

It can be used to append the multiple operands.

Concatenations are expressed as operands within the braces, with Commas separating
the operands.
Conditional Operator:
 Conditional operator having three operands.

 Syntax:
(Conditional Expression) ? (True Expression) : (False Expression) ;

 First, conditional expression is evaluated. If result is True. Then Evaluate True

Expression. Otherwise, evaluate False Expression.

Conditional operators are Nested.

Example:
assign out = (A==3)?(control?X:Y): (control?M:N);
Verilog_Data Types:

 Data type is a classification that specifies which type of value can be

assigned to a variable.

 It specifies which type of Mathematical Operation can be applied to a

variable

 Data Types

 Register

 Net
Register data type:
 Register can store/hold a value until next value assigned.

 It is not similar to the hardware register.

 It is commonly declared by the keyword is “reg”

 Default value of the reg data type is X (unknown value).

 Classification reg data tpyes are

Reg
Real
Integer
Time
Verilog_Register-Data Types:

 Reg (Most Widely used)

 Integer (Used for Loop Counting)

 real (Used to store Floating Point Numbers)

 time (Keeps track of simulation time)

10 Units Delay
Integer-Data Type:
 It is a General Purpose register data type declared by keyword “Integer”.

 Store the Values of Signed Quantities.

Examples: 0, 4, -7, 58, -45, etc.

 Generally Used for Counting Purpose.

 Synthesizable in Nature.

Default Value is “X”.

 Default Width is “32 bits”.

Real-data type:
 Allows to store Floating Point Value (Decimal & Scientific notation).
Examples: 3.4, -17.8, 0.7, -1.567, 5.654, etc.

 Declared by Keyword “real”.

 Not Synthesizable.

 Default Value is “0.0”

 Rounded-off to the nearest integer when it is assigned to an integer

variable.
Time-data type:
 It can be used to store simulation time.

 declared by keyword “Time”.

 Time Variable are “unsigned” in nature.

 Width is Specific. But, it is “ at least 64-bits”

 Not Synthesizable (used only test bench)

 Default value is “X”

It is a System
Function. It gives
Simulation Time
Net - data type:
 Nets represents the connection b/w two hardware elements.

 It can not be used to store the values (continuously driven).

 Default value of Net data type is “Z”

 Primary Keyword for Net data type is “wire”

 Classification of Net data types are

Wire
Wand
Wor
Tri
Triand
Trior
Trireg
Example-1:
In Assigned operation, Left
side Variable must be “net”
data type {“wire” data type}.

here, Sum &

Carry are
Continuously
Driven.
 Here, both the O/P of (A&B) and O/P of (C|D) are appearing
Example-2: at the same wire. So, O/P becomes In- deterministic. In-deterministic situation can
Simulator gets confused which value assigned to ‘Y’. be eliminated by inserting
AND or OR-Gate. Nothing
but, use “wand”
Verilog-Values & Strengths:
To Model the Functionality of real hardware, Verilog supports 04 Value
Levels & 08 Signal Strengths.

Value Levels Condition in Hardware Circuits

0 Logic Zero, False Condition
1 Logic One, True Condition
X Unknown Logic Value
Z High Impedance, Floating State
Example for Usage of Supply1 and Supply0:
Port Assignments:
 Three types of Port Assignments such as Input, Output & Inout.

 both Input & Output are Unidirectional Ports.

 Inout is Bidirectional Port.

 Input – variable data type is internally “net”, Externally “reg or net”

 Output – variable data type is internally “reg or net”, Externally “net”

 Inout - variable data type is “wire”

Verilog- Modules:

 A module is the basic building block in Verilog.

 A module can be an element (or) collection of lower level design blocks.

A module can provide required functionality to the higher level design

block through its port interface. But, it hides the internal implementation.

 It provides flexibility to modify the module internals without affecting

the rest of the design.
Module Instantiation:

Module instantiation is a process of creating object (instances) from a

module template.
for Examples
Construct 4*1 Mux using 2*1 Mux.
Construct Full Adder using Half Adder

Instantiation creates Hierarchy( Creates Module using Sub-Modules) in

Verilog description.

In Verilog, Nesting of Module is Illegal. That means one module definition
can not contain in another module definition. But, we can incorporate copies
of other module using module instantiation.
Verilog-Simulation:

Simulation is used to verify the functionality of digital design (Verilog Module or

RTL code) that can modeled using HDL like Verilog.

For Simulation purpose, we apply different input stimulus (Test Bench) to the
digital design at different time, to check whether RTL code behaves in a given
intended manner or not.
Verilog-Synthesis:

Synthesis is a process in which the digital design that is modeled by HDL (RTL code)
is translated into the implementation consisting of Logic Gates.

It is used to convert RTL code to Net list.

It is a just Optimal design.

 Test Bench not Required for Synthesis.

Design Methodologies:

Top-Down Design Methodology:

Flow of Design starts from Top level block to Bottom level block.

 Each Main Block divide into the Sub-blocks until reaches to the leaf cell
(smallest possible block).

Bottom-Up Design Methodology:

 Flow of Design starts from Bottom level block to Top level block.

 First identify Building block (Module (or) Leaf Cell). Combined them to form
bigger block (Macro cell). And then use macros to form Top level block.