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4-Assemble Language program-IAS-11-01-2024

The document discusses the organization and operation of the Von Neumann machine. It describes how the Von Neumann machine uses a central processing unit (CPU) that fetches instructions from memory and operates on data stored in memory. The CPU contains an arithmetic logic unit (ALU) for performing arithmetic and logic operations, and registers for temporary storage of data and instructions during processing. The CPU fetches instructions from memory one at a time and executes each instruction, reading operands from memory as needed before writing results back to memory.

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Harsh Goyal
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189 views8 pages

4-Assemble Language program-IAS-11-01-2024

The document discusses the organization and operation of the Von Neumann machine. It describes how the Von Neumann machine uses a central processing unit (CPU) that fetches instructions from memory and operates on data stored in memory. The CPU contains an arithmetic logic unit (ALU) for performing arithmetic and logic operations, and registers for temporary storage of data and instructions during processing. The CPU fetches instructions from memory one at a time and executes each instruction, reading operands from memory as needed before writing results back to memory.

Uploaded by

Harsh Goyal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Organization of Von Neumann machine

Dr.J.saira banu , Associate Professor, SCOPE, VIT University


Example Problem

Write an appropriate assembly language code for the


following operation and register transfer operation.
X=Y+Z
Where Z->40 bit data and Y->40 bit data

Assume that data variables ‘Y’ & ‘Z’ available at memory


locations 500 & 501 resly. And store the result in 600.
Assume the Program is stored in the location 1 onwards.

Dr.J.saira banu , Associate Professor, SCOPE, VIT University


ACAC
=7
3 MQ
MEMORY
1. LOAD M( 500), ADD M (501)
2. STOR M(600), (Other Ins)
.....
500. 3
501. 4 500
MBR
LOAD
ADD
M(X)
MBR= 500
M(X) 4501
3
(Other STOR
Ins) M(X)

PC 21
MAR 501
500
21
MBR LOAD
STOR
M(X)
M(600),
500,
3 ADD
4 (Other
M(X)
Ins) 501
IR LOAD
STOR
ADD M(X)
M(X)
IBR ADD
(Other
M(X)Ins)
501
AC 7
3 501
AddIBR
M(X) PC
PC←
Mar
MAR =←PC
21
=PC
3 M(X) 501
LOAD M(X) 500, ADD
4
STOR M(X) 500, (Other Ins)
IR MAR
MAR
MAR
MAR
add=500
=2
501
==5001
= 501
add == 500
add
add =12
IAS Computer AC MQ

MARPC
MBRM[MAR] Arithmetic & Logic Circuits
Input/output
IBRMBR<20..39> IBRMBR<20..39> Equipments
IRMBR<0..7> IRMBR<0..7>
MARMBR<8..19> MARMBR<8..19> MBR
MBRM[MAR] MBRAC
ACMBR M[MAR}MBR
IRIBR<0..7> IRIBR<0..7>
MARIBR<8..19> IBR PC
MBRM[MAR]
ACAC + MBR Main
PCPC+1 Memory
MARPC
IR
MBRM[MAR] MAR

Control
Circuits
IAS Computer Flow of Operation Flow-Chart

Dr.J.saira banu , Associate Professor, SCOPE, VIT University


Example Problem

Write an appropriate assembly language code for the


following operation and register transfer operation.
X=Y*Z
Where Z->40 bit data and Y->40 bit data
Result would be more than 40 bit.

Assume that data variables ‘Y’ & ‘Z’ available at memory


locations 801 & 802 . And X will be stored 803 onwards

Dr.J.saira banu , Associate Professor, SCOPE, VIT University


Practice problems

Write an Assembly language programming for the following expressions using IAS
computer Instruction set and interpret to the flow of IAS computer

1. A=(B-C)*D

2. A=B*(C+D)

3. A=(B-C)/D

4. A=B/(C+D)

5. A=(B+C-D)

6. A=(B*2)/2
Make necessary assumptions.
Dr.J.saira banu , Associate Professor, SCOPE, VIT University
Challenging Problem

Write an assembly language programming for the following code fragment and
Interpret to IAS computer flow of operations.
if(x=0)
c=a*b;
else
c=a/b;
Where
Data variables are avaible from loation address 500 onwards and program can
be stored at memory location 200 onwards.

Dr.J.saira banu , Associate Professor, SCOPE, VIT University

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