Chapter 1
Chapter 1
Introduction
Prepared by
Assist. Prof. Mohamed Ismail
Assist. Professor at Delta Higher Institute for Engineering &
Technology
Outlines
Why build Integrated Circuits (Ics)?
History of ICs.
Properties of VLSI.
Moore’s Law.
Components of IC.
VLSI MOS Transistors.
Scaling.
VLSI Design Considerations (Problems).
Mixed Signal VLSI.
Digital Design of VLSI.
Trends in VLSI.
Summary of Technology Trend.
MOSFET as a Capacitor.
References
?Why Build Integrated Circuits
Much smaller and consume less
power than the discrete component
needed to build electronic systems.
Much easier to design and
manufacture.
More reliable than discrete
components.
Improved performance because of
low cost more than complex circuitry.
History of ICs
1958 : First IC ( Flip-Flop using 2
transistors built by J.Kilby).
1960 : SSI (Small Scale Integration)
less than 100 components/chip.
1966 : MSI ( Medium Scale
Integration) more than 100
components/chip.
1969 : LSI (Large Scale Integration)
more than 1000 components/chip.
History of ICs Cont’d
1975 : VLSI (Very Large Scale
Integration) more than 104
components/chip.
1989 :ULSI(Ultra Large Scale
Integration) more than 106
components/chip.
2003 : GLSI (Giant Large Scale
Integration) more than 107
components/chip
Properties of VLSI
Compact.
Reliable.
Not expensive.
Moore’s Law
No. of components (transistors)
per chip doubles every [year, 18
months, or 2 years].
Components of IC
VLSI components may be included 4
inputs and 2 outputs.
Its Inputs are:
– Material research
– Device modeling
– Circuits and systems design
– Computer-aided design CAD
Simulation.
Its Outputs are:
– Technology Development.
– Applications as mobiles, robotics, etc.
VLSI MOS Transistors
Scaling
Assume all geometric dimensions
(horizontal & vertical) and voltage and
current are reduced by factor α.
Scaling Advantages:
– Reduced Si area.
– Reduced power dissipation.
– Increased the speed.
– Increased battery lifetime.
Scaling Disadvantages:
– Parasitic resistance.
– Parasitic capacitance.
– Short channel effect.
Scaling Cont’d
Scaling Process Summary:
Before
Effect After Scaling Amount
Scaling
Reduced L/α L Length
Reduced W/α W Width
ID / α ID Drain
Reduced
Current
J = ID / LW Current
Increased ΑJ
Density
The Same EDS = VDS / L EDS = VDS / L Electric Field
VLSI Design Considerations
Si Area.
Power Dissipation.
Delay Time.
Speed.
Testability.
Cost: [Die area, Packaging, Testing, …]
Time to Market.
Performance: [Optimization requirements
for high performance].
Design Complexity.
Mixed Signal VLSI
Mixed A/D VLSI:
– As ISDN (Integrated Service Digital Network).
– The analog part provides the I/O interface to
the core of the chip which is digital.
Mixed D/A VLSI :
– As ANN (Artificial Neural Network).
– The digital part provides the I/O interface to
the core of the chip which is analog.
Digital Design of VLSI
Trends in VLSI
Transistor:
– Smaller, faster, less power.
Interconnect:
– Less resistance, faster, longer.
Yield:
- Smaller die size, higher yield.
Summary of Technology Trend
Processor:
– Logic capacity increases by about 30% per
year.
– Clock frequency increases by about 20% per
year.
– Cost / function decreases by about 20% per
year.
Memory:
– DRAM capacity increases by about 60% per
year (4x every 3 years).
– Speed increases by about 10% per year.
– Cost / bit decreases by about 25% per year.
MSFET as a Capacitor
MSFET as a Capacitor Cont’d
10-12
References
N.West and D.Harris, CMOS VLSI Design.