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M5 Part1

The document discusses key aspects of semiconductor memories including area, access time, and power consumption. It describes the system timing considerations for reading and writing data to storage elements using a two-phase non-overlapping clock signal. Finally, it provides an overview of common memory architectures like DRAM and SRAM, focusing on their organization, operation principles, and tradeoffs between area, power consumption, and refresh requirements.

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Rohit Vinayak Hegde
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34 views25 pages

M5 Part1

The document discusses key aspects of semiconductor memories including area, access time, and power consumption. It describes the system timing considerations for reading and writing data to storage elements using a two-phase non-overlapping clock signal. Finally, it provides an overview of common memory architectures like DRAM and SRAM, focusing on their organization, operation principles, and tradeoffs between area, power consumption, and refresh requirements.

Uploaded by

Rohit Vinayak Hegde
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Semiconductor Memories

CMOS VLSI DESIGN 1


Key aspects

Area: depends on no of bits stored


Access time:speed
Power consumption
SYSTEM TIMING CONSIDERATIONS

1. A two-phase non-overlapping clock signal is assumed to be


available, and this clock alone will be used throughout the
system.
2. Clock phases are to be identified as ø1 and ø2 where ø1 is
assumed to lead ø2.
3. Bits (or data) to be stored are written to registers, storage
elements, and subsystems on ø1 of the clock; that is, write
signals WR are Anded with ø1.
4. Bits or data written into storage elements may be assumed
to have settled before the immediately following ø2 signal,
and ø2 signals may be used to refresh stored data where
appropriate.

6
SYSTEM TIMING CONSIDERATIONS

5. In general, delays through data paths, combinational logic,


etc. are assumed to be less than the interval between the
leading edge of ø1 of the clock and the leading edge of the
following ø2 signal.
6. Bits or data may be read from storage elements on the next
ø1 of the clock; that is, read signals RD are Anded with ø1.
Obviously, RD and WR are generally mutually exclusive to
any one storage element.

7
Conceptual random access
memory array organization
Bit lines
DRAM
4T DRAM

Bitline is where you place the data to be stored during a write operation and
from where you read the stored data during a read operation.
Wordline is the one that activates cells based on the address input both while
reading and writing.
Access transistor the process of data read out from a cell begins with the
activation of the access transistor to that cell.
3T TRANSISTOR
1TRANSISTOR
SRAM
6T SRAM:
Periodic refreshment not required
Area more
PD less
6T SRAM: Read 0

1V
0V
6T SRAM: write 0 if 1 is stored
Memory architecture
Leakage Is
Sense Amplifier

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