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STA Basics by Atun1

STA is a method to validate timing metrics of a design such as maximum frequency, setup violations, and path delays. First, the design is broken down into timing paths consisting of timing arcs between valid startpoints like inputs and endpoints like outputs of synchronous devices. Then, each path's delay is calculated and checked for timing violations like setup violations where data doesn't reach the next flop in time. Timing paths model the delay of nets and cells which depends on input slew and output load. Liberty files contain cell delay models for different processes, voltages, and temperatures.

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Nishanth Gowda
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93 views10 pages

STA Basics by Atun1

STA is a method to validate timing metrics of a design such as maximum frequency, setup violations, and path delays. First, the design is broken down into timing paths consisting of timing arcs between valid startpoints like inputs and endpoints like outputs of synchronous devices. Then, each path's delay is calculated and checked for timing violations like setup violations where data doesn't reach the next flop in time. Timing paths model the delay of nets and cells which depends on input slew and output load. Liberty files contain cell delay models for different processes, voltages, and temperatures.

Uploaded by

Nishanth Gowda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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STA Basics by Atun

25th March 2023


What is STA ?
• It just a method to validate the performance or timing metrices of a design.
• Timing Metrices refers to Max freq achieved , setup violations, hold violations , path
delay, transitions, pulse width, etc

What happens in STA ?


• First design is broken down into timing paths.
• Then each of theses paths are timed(delay for each of the path is calculated)
• After the path is timed, it is checked for all types of timing violation.
So what is a timing path ?
• It’s path in the circuit with a valid startpoint and
valid endpoint on which timing analysis is done.
• Valid startpoints : input ports and clock pins of
synchronous devices
• Valid endpoints : output ports and data input
pins of synchronous devices. How many
• Timing paths consists of Timing arcs. timing paths
are there in
the above
Setup and hold concept of a flop
A B
Setup check Hold check
• When the tool performs a hold check, it verifies that the
• when the tool performs a setup check, it verifies that the data launched from FF1 reaches FF2 no sooner than the
data launched from FF1 reaches FF2 within one clock capture clock edge for the previous clock cycle.
cycle before the data gets captured by the next clock • This check ensures that the data already existing at the
edge at FF2. input of FF2 remains stable long enough after the clock
• If the data path delay is too long, it is reported as a edge that captures data for the previous cycle. A hold
violation can occur if the clock path has a long delay.
timing violation.

Data from FF1/CP to FF2/D must satisfy setup and hold constraints

CLK at FF1/CP

Data at FF2/D
th tsu
CLK at FF2/CP
Delay calculation
• Timing path consists of nets and cell, delay of each path is net delay +
cell delay.
• Cell delays depends on input tran(slew ) and output load.
• Net delay or parasitic delay is a function of Cnet & Rnet.
Understanding Liberty Data
• .Lib or liberty file models the delay, Power, EM, noise.
• These are generated through characterization and for each PVT there are
different .lib files.
• Lets focus on Delay information in the .lib files
Sample Liberty file
Cell (…..)
……
Timing (){
related_pin : “CK”
timing_sense : positive_unate;
timing_type : combinational;
when : "!EN&SE";
Cell_rise (timing_table1)
Index 1(………..)
Index2 (……….)
Values (………….
……………..)

Index 1 consists of slew/tran values, Index 2 has cap values, The values is a look up
table, which has delay values correcponding to each tran and slew .
Clocks
A clock synchronizes the design and triggers the sequential elements.

Types of clock.
Real and Virtual.

Some clock concepts to discuss

Clock Jitter
Skew
PVT ( Process, Voltage, Temperature)
• We want our chips to function properly everywhere.
• Process, Voltage and temperature impact delay and Power.
• Thank you

• Q&A

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