Unit IV - Sequential Logic

Syllabus Unit IV
Sequential Logic:
• Introduction: Sequential Circuits. Difference between combinational
circuits and sequential circuits
• Flip- flop: SR, JK, D, T; Preset & Clear, Master and Slave Flip Flops
their truth tables and excitation tables, Conversion from one type to
another type of Flip Flop.
• Application of Flip-flops: Bounce Elimination Switch, registers,
counters.
• Registers: Buffer register; shift register;
• Counters: Asynchronous counter. Synchronous counter, ring
counters, BCD Counter, Johnson Counter, Modulus of the counter
(IC 7490), Pseudo Random Binary Sequence Generator, Sequence
generator and detector
Books to Refer
Text Books:

Chapter 12 from

R. Jain, “Modern Digital Electronics”, 3rd Edition, Tata McGraw-Hill,

2003, ISBN0 – 07 – 049492 – 4

Chapter 13 from

Stephen Brown, Zvonko Vranesic “ Fundamentals of Digital Logic

with VHDL Design” Mcgraw-Hill

Reference Book:

John Yarbrough, “Digital Logic applications and Design” Thomson

Lab Assignments
B. Sequential Circuit Design

1. Flip flops, Registers and Counters (Study and Write up

only).
2. 4-bit Multiplier / Divider (Study and Write up only).
3. Ripple counter using flip-flops.
4. Sequence generator using JK flip-flop.
5. Sequence detector using JK flip-flop.
6. Up-down counter using JK flip-flop.
7. Modulo N counter using 7490 & 74190 (N>10).
8. Pseudo random number generator.
9. Design of a barrel shifter.
Sequential Logic:

• Introduction: Sequential Circuits. Difference between

combinational circuits and sequential circuits
• Flip- flop: SR, JK, D, T; Preset & Clear, Master and
Slave Flip Flops their truth tables and excitation tables,
Conversion from one type to another type of Flip Flop.
• Application of Flip-flops: Bounce Elimination
Switch, registers, counters.
• Registers: Buffer register; shift register;
• Counters: Asynchronous counter. Synchronous
counter, ring counters, BCD Counter, Johnson Counter,
Modulus of the counter (IC 7490), Pseudo Random
Binary Sequence Generator, Sequence generator and
detector
Sequential Circuits
Differences
• Combinational • Sequential circuits
circuits 1. Output depends on
1. Output depends on present inputs as well as
present input only previous inputs.
2. Memory element is
2. It does not have memory necessary
element 3. Clock input is require
3. Clock input is not 4. Ex: Flip flops, Shift
require Registers, Counters
4. EX: Adders,
Subtractors,
Code Convertors
Sequential Logic:

• Introduction: Sequential Circuits. Difference between

combinational circuits and sequential circuits
• Flip- flop: SR, JK, D, T; Preset & Clear, Master and Slave Flip
Flops their truth tables and excitation tables, Conversion from one
type to another type of Flip Flop.
• Application of Flip-flops: Bounce Elimination Switch, registers,
counters.
• Registers: Buffer register; shift register;
• Counters: Asynchronous counter. Synchronous counter, ring
counters, BCD Counter, Johnson Counter, Modulus of the counter
(IC 7490), Pseudo Random Binary Sequence Generator,
Sequence generator and detector
1 Bit Memory Cell
Properties

• The output Q and Q̅̅ are always

Complementary.
A1 G1 Q • The Circuit has two stable
State.(i.e. Q=1 Set State and
Q=0 Reset State).
• The Circuit continues to
A2
remain in the same state
G2 Q referred to as Memory.
• The information is latched or
Cross Couple Inverter s as Memory locked in this circuit ,so it is
Element also referred as Latch.
1 Bit Memory Cell with input
• IF S=R=0 Circuit will be same
as prev.
• IF S=1 & R=0 then Q=1
• IF S=0 & R=1 then Q=0
• IF S=R=1 , then both the
outputs Q and Q̅ will try to
become 1 which is not allowed
and therefore this input
condition is prohibited.
A Clocked S-R Flip Flop

Input Input Output

Sn Rn Qn+1
0 0 Qn
1 0 1
0 1 0
1 1 ?
What is a JK Flip-flop?

• A flip-flop is a circuit that has two stable states

and can be used to store state information.

• The flip-flop can be made to change state by

signals applied to one or more control inputs and
will have one or two outputs.
 JK Terminology/Structure
Has 5 inputs named:
J(set),K(reset), PR, CLR, and CLK

Has 2 outputs: Q and Q’

PR = Preset
CLR = Clear
CLK = Clock

Set: when it stores a binary 1

Cleared (reset): when it stores a binary 0
Outputs
The Q output is the primary output.
This means that the binary bit
stored in the flip-flop, 1 or 0, is
the same as Q.

The Q’ output is the

opposite binary bit value
that is stored in Q.

The PR and CLR inputs always

override the J,K inputs.
Inputs: PR and CLR

A low at the PR input sets Q = 1

A low at the CLR input sets Q = 0

Inputs: J and K
The logic states applied to the J and K inputs cause
the flip-flop to operate 4 different ways.

The way the logic state is applied to J and K is called

Mode of Operation.

The mode of operation refers to the condition of the

flip-flop as it prepares for the positive clock pulse.
Four Modes Of Operation

The 4 modes of operation are:

hold, set, reset, toggle

J K Q Q’ Mode
0 0 Q Q’ Hold
1 0 1 0 Sets JK contains an internal
Active Low SR latch.
0 1 0 1 Resets
1 1 Q’ Q Toggle
Review: Truth Table for NAND

2 Inputs: 3 Inputs:

A B X A B C X
0 0 1 0 0 0 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
1 1 0 0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Mode of Operation: Hold
Hold: no change in Q.

J K Q Q’ Orig. Q Orig. Q’
0 0 0 1 0 1
Mode of Operation: Set
Set: Q = 1.

J K Q Q’ Orig. Q Orig. Q’
1 0 1 0 0 1
Mode of Operation: Reset
Reset: Q = 0.

J K Q Q’ Orig. Q Orig. Q’
0 1 0 1 1 0
Mode of Operation: Toggle
Toggle: Q = Q’.

J K Q Q’ Orig. Q Orig. Q’
1 1 1 0 0 1
Mode of Operation: Toggle again
Toggle: Q = Q’.

J K Q Q’ Orig. Q Orig. Q’
1 1 0 1 1 0
Overview: During a time period
Characteristic Equation

Q J K Q(t + 1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1 Characteristic Equation:
1 1 1 0
Q(t+1) = J.Q’+ K’.Q
If only one slide to remember…
Characteristic Equation:

Q(t+1) = J.Q’+ K’.Q

Q is the primary output.

J K Q Q’ Mode
0 0 Q Q’ Hold SR Latch:
1 0 1 0 Sets
A ‘0’ at the set or the
0 1 0 1 Resets
reset will either set or
1 1 Q’ Q Toggle reset the value of Q.
Race Around Condition
Master Slave Flip Flop
Input Output waveform of Mater Slave flip flop
D-Type Flip Flop
• If we use only middle two rows of the truth table
of S-R or J-K Flip flop, we obtain D- tyoe of Flip
flop
J K Q
0 0 Q
1 0 1
0 1 0
1 1 Q’

D Q
0 0
1 1
T Type Flip Flop
• In J K Flip Flop , if J=K, the resulting Flip flop is
referred to as a T- type Flip Flop.
P J K Q
r
0 0 Q
1 0 1
0 1 0
1 1 Q’
Clk

D Q
0 Q
1 Q’
Cr
Preset & Clear
• When the power is switched on the state of the
circuit is uncertain.(i.e. 0 or 1)
• In many application it is desired to initially set
or reset the Flip Flop to initial state.
• This is accomplished by using direct or
asynchronous inputs referred to as preset(Pr)
and clear(Cr) inputs.
• These inputs may be applied at any time
between clock pulses and are not in synchronism
with
SR flip-flop with Preset & Clear
Preset(Pr)

Inputs Output Operation

Performed

Clk Cr Pr Q
CLK
1 1 1 Qn+1 Normal FF

0 0 1 0 Clear

0 1 0 1 Preset
Clear (Cr)

An S-R Flip- Flop with Preset and Clear

Excitation Tables
• The truth table of Flip Flop is also referred to as
the characteristic table.

• Sometimes there is need to find input condition

from the given output condition , tabulation of
these condition is known as excitation table.
S R Flip Flop
SR truth table Next state table

S R Qn+1 S R Qn Qn+1
0 0 Qn 0 0 0 0
0 1 0 0 0 1 1
1 0 1
0 1 0 0
1 1 ?
0 1 1 0

SR excitation table 1 0 0 1
1 0 1 1
Qn Qn+1 S R
1 1 0 ?
0 0 0 X
1 1 1 ?
0 1 1 0
1 0 0 1
1 1 X 0
J K Flip Flop
JK truth table Next state table

J K Qn+1
J K Qn Qn+1
0 0 Qn
0 1 0 0 0 0 0

1 0 1 0 0 1 1
1 1 Qn’ 0 1 0 0
0 1 1 0
JK excitation table 1 0 0 1
1 0 1 1
Qn Qn+1 J K
1 1 0 1
0 0 0 X
1 1 1 0
0 1 1 X
1 0 X 1
1 1 X 0
D Flip Flop
D truth table Next state table

D Qn+1 D Qn Qn+1
0 0 0 0 0
1 1 0 1 0
1 0 1
1 1 1
D excitation table
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
T Flip Flop
T truth table Next state table

T Qn+1 T Qn Qn+1
0 Qn 0 0 0
1 Qn’ 0 1 1
1 0 1
1 1 0
T excitation table
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
Conversion from one Flip Flop to Another
Conversion of Flip Flops
• SR to JK
• SR to D
• SR to T
• JK to D
• JK to T
• D to T
• T to D
• JK to SR
• T to SR
• D to JK
T Flip-Flop to D Flip-Flop
Input Present Next State Flip- Flop
State input
D Qn Qn+1 T
0 0 0 0
0 1 0 1
1 0 1 1
1 1 1 0

Excitation table of T Flip Flop

Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
T Flip-Flop to D Flip-Flop
Qn 0 1
D
0 0 1

1 1 0

T = D Q’ + D’ Q
D
D’

T
D Flip Flop to JK Flip Flop
Input Input Present Next Flip
State State Flop
input
J K Qn Qn+1 D
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 0
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 0 0
D Flip-flop to JK Flip Flop
Q
0 1 Q 0 1
JK
JK D Q+
0 0 1 0 0 1
0 0 0 0 0 0 0 0
01 1 0 01 1 0 1 1
11 1 1 11 1 1
10 10

D = J Q’ + K’ Q

Q
J
D

K
Q’
T Flip Flop to JK Flip Flop
Excitation Table of T FF
Inpu Inpu Prese Next Flip
t t nt State Flop
State input Qn Qn+1 T
J K Qn Qn+1 T 0 0 0
0 0 0 0 0 0 1 1
0 0 1 1 0 1 0 1
0 1 0 0 0 1 1 0
0 1 1 0 1
1 0 0 1 1
1 0 1 1 0
1 1 0 1 1
1 1 1 0 1
T Flip-flop to JK Flip Flop
Q Q+
Q 0 1
0 1 JK Q+
JK
JK
T Q+
0 0 0 0 0 0
0 Q
0 0 1 0 0 1 0
0 0 Q
01 1 1 01 1 1 01
1 1 Q’
11 1 0 11 1 0 10
Q’
10 10 11

T = J Q’ + K Q

Q
J
T

K
Q’
JK Flip Flop to T Flip Flop
Input Present Next State Flip Flop Flip Flop
State Input Input

T Qn Qn+1 JA KA
0 0 0 0 X
0 1 1 X 0
1 0 1 1 X
1 1 0 X 1

Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Implement T Flip-flop by JK Flip-flop
Q
T 0 1 Q J K
Q+
0 0 1 0 0 X
1 1 0 0 1 X
01 X 1
10 X 0
11
Q Q
T 0 1 T 0 1

0 X 0 X 0
0
1 1 X 1 X 1

J=T K=T
Sequential Logic:

• Introduction: Sequential Circuits. Difference between combinational

circuits and sequential circuits
• Flip- flop: SR, JK, D, T; Preset & Clear, Master and Slave Flip Flops
their truth tables and excitation tables, Conversion from one type to
another type of Flip Flop.
• Application of Flip-flops: Bounce Elimination Switch, registers,
counters.
• Registers: Buffer register; shift register;
• Counters: Asynchronous counter. Synchronous counter, ring counters,
BCD Counter, Johnson Counter, Modulus of the counter (IC 7490),
Pseudo Random Binary Sequence Generator, Sequence generator
and detector
Bounce Elimination Switch
• Mechanical switches are employed digital
systems as input devices by which digital
information is entered into the system.

• In Sequential circuit , if 1 is to be entered

through a switch , then the switch is thrown to
the corresponding position. The output oscillates
between 0 and 1 creates difficulty in the
operation of system. This problem is eliminated
by Bounce Elimination Switch.
Switch Denouncer
Registers
• A register s composed of group of Flip Flops to
store group of bits.

• For storing N bit word , N number of Flip Flops

are required.

• One Flip Flop is required for storing each bit.

• There are different way to enter data in registers.

Counters
• Digital counters are often needed to count
events.

• The counter are also composed of Flip Flops.

• A circuit with n Flip Fops has 2n possible states

Sequential Logic:

• Introduction: Sequential Circuits. Difference between combinational

circuits and sequential circuits
• Flip- flop: SR, JK, D, T; Preset & Clear, Master and Slave Flip Flops
their truth tables and excitation tables, Conversion from one type to
another type of Flip Flop.
• Application of Flip-flops: Bounce Elimination Switch, registers, counters.
• Registers: Buffer register; shift register;
• Counters: Asynchronous counter. Synchronous counter, ring counters,
BCD Counter, Johnson Counter, Modulus of the counter (IC 7490),
Pseudo Random Binary Sequence Generator, Sequence generator and
detector
Registers
• Registers hold larger quantities of data than individual flip-
flops.

▫ Registers are central to the design of modern processors.

▫ There are many different kinds of registers.

• A register is an extension of a flip-flop that can store

multiple bits.

• Registers are commonly used as temporary storage in a

processor.

▫ They are faster and more convenient than main memory.

▫ More registers can help speed up complex calculations.
Types of Registers
• Buffer Register

• Shift Register
i. Serial In Serial Out (SISO)
ii. Serial In Parallel Out (SIPO)
iii. Parallel In Serial Out (PISO)
iv. Parallel In Parallel Out (PIPO)
v. Bidirectional Shift Register
vi. Universal Shift Register
Buffer Register

• Input • Input • Input

• D Q • D Q • D Q

• Q • Q • Q

• Output • Output • Output

Shift Registers
• SISO: Serial In, Serial Out 10110 10110

10110

• SIPO: Serial In, Parallel Out 10110

10110

• PISO: Parallel In, Serial Out

10110
10110

• PIPO: Parallel In, Parallel Out

10110
 Regis
ters

Shift Register Construction 1.59

• Shift registers are comprised of D Flip-Flops that

share a common clock input.

D Q D Q D Q

Q Q Q
 Regis

SISO Flip-Flop Shift Register ters

1.60

• a Serial In Serial Out shift register has a single

input and a single output

Input D Q D Q D Q Output

Q Q Q
 Regis

SIPO Flip-Flop Shift Register ters

1.61

• A Serial In Parallel Out shift register has a single

input and access to all outputs
Output Output Output

Input D Q D Q D Q

Q Q Q
 Regis
PISO Flip-Flop Shift Register ters
1.62

• A Parallel In Serial Out shift register requires

additional gates, and the parallel input must
revert to logic low.
Input
Input Input
Output

D Q D Q
D Q
Q Q
Q
 Regis

PIPO Flip-Flop Shift Register ters

1.63

• A Parallel In Parallel Out register has the

simplest configuration. It represents a memory
device.
Input Input Input

D Q D Q D Q

Q Q Q

Output Output Output

Bidirectional Shift Register
Bidirectional Shift Register
 Regis
ters
1.66
Universal Shift Registers

• If the register has both shifts (right

shift and left shift) and parallel load
capabilities, it is referred to as
universal shift register.
 Regis
Shift Register Applications ters
1.67

▫ Temporary data storage.

▫ Bit manipulation.
▫ Serial to parallel convertor.
▫ Parallel to serial convertor.
▫ Computer and Data Communications.
▫ Serial and Parallel Communications.
▫ Multi-bit number storage.
▫ Sequence generator.
▫ Sequence Detector.
▫ Logical operations.
Sequential Logic:

• Introduction: Sequential Circuits. Difference between combinational

circuits and sequential circuits
• Flip- flop: SR, JK, D, T; Preset & Clear, Master and Slave Flip Flops
their truth tables and excitation tables, Conversion from one type to
another type of Flip Flop.
• Application of Flip-flops: Bounce Elimination Switch, registers,
counters.
• Registers: Buffer register; shift register;
• Counters: Asynchronous counter. Synchronous counter, ring
counters, BCD Counter, Johnson Counter, Modulus of the counter
(IC 7490), Pseudo Random Binary Sequence Generator, Sequence
generator and detector
Counter
• A Counter is a register capable of counting the
number of clock pulses arriving at its clock input.

• n bit counter has n flip flops and it has 2n distinct

states with maximum count of 2n -1.

• Types of Counter
1. Synchronous Counter
2. Asynchronous Counter
Differences
Asynchronous Counter Synchronous Counter
• Output of the first flip flop • No connection between output
drives the clock for the next of first flip flop and clock input
flip flop. of the next flip flop.
• All the flip flops are not • All the flip flops are clocked
clocked simultaneously. simultaneously.
• Logic circuit is very simple. • Logic circuit is complex.
• These counters are slow • These counters are fast.
because of propagation delay.
Ripple/Asynchronous Counter
4 Bit asynchronous down counter
Asynchronous Up/ Down Counter
Truth Table
Input Input Input Outp
ut
Y=Q’ for down
M Q Q’ Y counting
0 0 0 0
0 0 1 1
Y=Q for up counting
0 for1 0 0
0 1 1 1
1 K0
Map Equation0for Y=M’Q’+MQ
0
1 0
UP/DOWN’ = Y1 0
1 1 0 1
1 1 1 1
3 bit Synchronous Up/Down Counter
Counter has 8 states i.e N=8
2n >= N
n = no. of Flip Flop= 3
Control Input for Flip-flop
input M QC QB QA QC+1 QB+1 QA+1 J C KC J B KB J A KA

0 0 0 0 0 0 1 0 X 0 X 1 X
0 0 0 1 0 1 0 0 X 1 X X 1
0 0 1 0 0 1 1 0 X X 0 1 X
0 0 1 1 1 0 0 1 X X 1 X 1
0 1 0 0 1 0 1 X 0 0 X 1 X
0 1 0 1 1 1 0 X 0 1 X X 1
0 1 1 0 1 1 1 X 0 X 0 1 X
0 1 1 1 0 0 0 X 1 X 1 X 1
1 1 1 1 1 1 0 X 0 1 X 1 X
1 1 1 0 1 0 1 X 0 X 0 X 1
1 1 0 1 1 0 0 X 0 X 1 1 X
1 1 0 0 0 1 1 X 1 0 X X 1
1 0 1 1 0 1 0 0 X 1 X 1 X
1 0 1 0 0 0 1 0 X X 0 X 1
1 0 0 1 0 0 0 0 X X 1 1 X
1 0 0 0 1 1 1 1 X 1 X X 1
Logical diagram of 3 bit Synchronous Counter
Decade Binary Counter/Modulo N counter
• IC 7490 is a decade binary counter
Internal Diagram of IC 7490
Function table 7490

Reset Input Output

Ro(1) Ro(2) Rg(1) Rg(2) QD QC QB QA
H H L X L L L L
H H X L L L L L
X X H H H L L H
X L X L COUNT
L X L X COUNT
L X X L COUNT
X L L X COUNT
Design MOD 6 counter using IC 7490.
• Theoretical Method
Clock count states QD QC QB QA Reset
input

0 0 0 0 0 0
1 0 0 0 1 0
2 0 0 1 0 0
3 0 0 1 1 0
4 0 1 0 0 0
5 0 1 0 1 0
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
Design MOD 6 counter using IC 7490.
Logical Diagram for Mod 6 Counter
Divide by 20 counters using IC 7490

• Logical Method :-

• MOD 20 COUNTER: -We know that One IC can

work as mod-10 BCD counter. Therefore we need
two ICs. The counter will go through 0-19 & should
be reset on state 20 i.e.
QD QC QB QA QD QC QB QA
0 0 1 0 0 0 0 0

7490(1) 7490(2)
Logical Diagram for Mod 20 counter
Ring Counter
• A ring counter takes the serial output of the last Flip-Flop of
a shift register and provides it to the serial input of the first
Flip-Flop.
Timing Sequence of 4 bit Ring Counter
Johnson Counter / Twisting Ring / Switch
Tail Counter

• A Johnson Counter re-circulates the last flip-flop Q

(inverted) output back to the input of the first Flip-
Flop. It doesn’t require an initialization value, and will
provide a predictable output state sequence.
Sequence Generator
• A Sequence Circuit, Which generates a
prescribed sequence of bits in synchronism with
a clock, is referred to as sequence generator.
Problem Statement
• Design sequence generator to go through the
following states by using J K flip-flop
Present Next state Jn Kn
state
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Present Next state A B C

states
QA QB QC QA+ QB+ QC+ JA KA JB KB JC KC
1 1 1
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 1 0 X 1 X X 0
0 1 0 X X X X X X X X X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 1 0 X 0 1 X 0 X
1 0 1 X X X X X X X X X
1 1 0 0 0 0 X 1 X 1 0 X
1 1 1 X X X X X X X X X
Sequence Generator
Sequence Detector

• A Sequence Circuit, Which detects a prescribed

sequence of bits in synchronism with a clock, is
referred to as sequence detector.
Problem Statement
• Design sequence detector using J K flip-flop to
detect the following sequence: 1001
• Solution: State diagram
Present Next Jn Kn
state state
0
0
0
1
0
1
X
X
State Transition Table
1 0 X 1
1 1 X 0

Present states Next state FF 1 FF 0

Q1 Q0 X Q1+1 Q0+1 Z J1 K1 J0 K0
0 0 0 0 0 0 0 X 0 X
0 0 1 0 1 0 0 X 1 X
0 1 0 1 0 0 1 X X 1
0 1 1 0 1 0 0 X X 0
1 0 0 1 1 0 X 0 1 X
1 0 1 0 1 0 X 1 1 X
1 1 0 0 0 0 X 1 X 1
1 1 1 0 1 1 X 1 X 0
K Map
Sequence Detector
Pseudo random number generator
• It is application of Shift Register.

• It consist of number of Flip flop and

combinational circuit for providing a suitable
feedback.

• The feed back circuit can be as simple as Ex-OR

gate
Assume initial state of shift register is
Q3 Q2 Q1 Q0 = 0 0 1 1.
Clock Pulse PBRS
Number Shift Register EX-OR Gate Sequence
Q3 Q2 Q1 Q0 Q3 ÅQ2 Q3
0 0 0 1 1  0
1 0 1 1 0 0  1=1 0
2 1 1 0 1  =0 1
3 1 0 1 0 1 0=1 1
4 0 1 0 1 01=1 0
5 1 0 1 1 1 0=0 1
6 0 1 1 1  0
7 1 1 1 1 =0 1
8 1 1 1 0 =0 1
9 1 1 0 0 =0 1
10 1 0 0 0 10= 1
11 0 0 0 1  0
12 0 0 1 0  0
13 0 1 0 0 01=1 0
14 1 0 0 1 10=1 1
15 0 0 1 1  0
16 0 1 1 0 01=1 0
17 1 1 0 1 =0 1
Logical Diagram of 74194 As a PBRS
Generator
PBRS generator
• The PBRS generator cannot generate a truly
random sequence because this structure is a
deterministic structure. This is reason why the
sequence repeats itself.
• The maximum length of sequence will be 2N-1.
• Periodic sequence has a period of 2N-1, where N
is the number of Flip Flop in shift register.
• Thus the sequence repeats after 2N-1 clock cycle.
• Used in Data Encryption.