UNIT- 1

The Microprocessor & its

Architecture

Dr. REKHA.K.S.
Associate Professor,
Dept of CS&E,
NIE,MYSURU
Chapter Objectives
is to study

⚫ The architecture of Intel microprocessors

⚫ Describe function and purpose of each program-
visible register in the 8086-Core2 microprocessors
⚫ flag register and the purpose of each flag bit.
⚫ Addressing modes for the real, protected, and flat
modes of operation.
Real Mode
⚫ Real mode, also called real address mode, is an
operating mode of all x86-compatible CPUs.
⚫ Real mode operation allows the microprocessor to
address only the first 1M byte of memory space(DOS
memory system)
⚫ real mode always correspond to real locations in
memory.
⚫ Real mode provides no support for memory protection,
multitasking, or code privilege levels.
Protected Mode
⚫ Protected mode memory addressing (80286 and above)
allows access to data and programs located above the
first 1M byte of memory, as well as within the first 1M
byte of memory.
⚫ Protected mode is where Windows operates.
FLAT MODE
⚫ Flat memory model or linear memory model refers to a
memory addressing paradigm in which "memory
appears to the program as a single contiguous
address space.

⚫ The CPU can directly (and linearly) address all of the

available memory locations
The Programming Model
⚫ 8086 through Core2 considered
⚫ program visible.
⚫ registers are used during programming and are
specified by the instructions
⚫ program invisible.
⚫ not addressable directly during applications
programming
⚫ Figure 2–1 The programming model of the 8086
through the Core2 microprocessor including the
64-bit extensions
Multipurpose Registers
⚫ RAX - a 64-bit register (RAX), a 32-bit register
(accumulator) (EAX), a 16-bit register (AX), or as
either of two 8-bit registers (AH and AL).

⚫ The accumulator is used for instructions such as

multiplication, division, and some of the adjustment
instructions.
⚫ RBX, addressable as RBX, EBX, BX, BH, BL.
⚫ BX register (base index) sometimes holds offset
address of a location in the memory system in all
versions of the microprocessor
⚫ RCX, as RCX, ECX, CX, CH, or CL.
⚫ a (count) general-purpose register that also holds
the count for various instructions
⚫ RDX, as RDX, EDX, DX, DH, or DL.
⚫ a (data) general-purpose register
⚫ holds a part of the result from a multiplication
or part of dividend before a division
⚫ RBP, as RBP, EBP, or BP.
⚫ points to a memory (base pointer) location
for memory data transfers
⚫ RDI addressable as RDI, EDI, or DI.
⚫ often addresses (destination index) string
destination data for the string instructions
⚫ RSI used as RSI, ESI, or SI.
⚫ the (source index) register addresses source string
data for the string instructions
⚫ like RDI, RSI also functions as a general-
purpose register
⚫ R8 - R15 data are addressed as 64-, 32-, 16-, or 8-bit
sizes and are of general purpose
Special-Purpose Registers
⚫ Include RIP, RSP, and RFLAGS
⚫ segment registers include CS, DS, ES, SS, FS, and GS
⚫ RIP addresses the next instruction in a section of
memory.
⚫ defined as (instruction pointer) a code segment
⚫ RSP addresses an area of memory called
the stack.
⚫ the (stack pointer) stores data through this pointer
⚫ RFLAGS indicate the condition of the microprocessor
and control its operation.
⚫ Figure 2–2 shows the flag registers of all versions of the
microprocessor
Flag bits
⚫ C (carry) holds the carry after addition or borrow
after subtraction.
⚫ also indicates error conditions
⚫ P (parity) is the count of ones in a number expressed
as even or odd. Logic 0 for odd parity; logic 1 for even
parity.
⚫ if a number contains three binary one bits, it has
odd parity; If a number contains no one bits, it
has even parity
⚫ A (auxiliary carry) holds the carry (half-carry) after
addition or the borrow after subtraction between bit
positions 3 and 4 of the result.
⚫ Z (zero) shows that the result of an arithmetic or
logic operation is zero.
⚫ S (sign) flag holds the arithmetic sign of the result after
an arithmetic or logic instruction executes.
⚫ T (trap) The trap flag enables trapping through an
on-chip debugging feature.
⚫ If T flag is enabled(1),the microprocessor interrupts
the flow of the program on condition as indicated by
debug registers and control registers.
⚫ If T flag is logic 0, the trapping feature is disabled
⚫ I (interrupt) controls operation of the INTR (interrupt
request) input pin.
⚫ If I=1, the INTR pin is enabled, If I=0 the INTR pin is
disabled.

⚫ D (direction) selects increment or decrement mode for

the DI and/or SI registers during string instructions.
⚫ If D=1,the registers are automatically decremented; If
D=0, the registers are automatically incremented.
⚫ The D flag is set with STD(set Direction) and cleared with
the CLD (clear direction) instructions.
⚫ O (overflow) occurs when signed numbers are added or
subtracted.
⚫ an overflow indicates the result has exceeded
the capacity of the machine

⚫ IOPL used in protected mode operation

to select the privilege level for I/O devices
⚫ If the current privilege level is higher or more trusted than
the current privilege level, an interrupt occurs,causing
execution to suspend.
⚫ IOPL of 00 is highest is more trusted
⚫ IOPL of 11 is the lowest one least trusted.
⚫ NT (nested task) flag indicates the current task is
nested within another task in protected mode
operation.
⚫ RF (resume) used with debugging to control
resumption of execution after the next instruction.
⚫ VM (virtual mode) flag bit selects virtual mode
operation in a protected mode system.
⚫ A virtual mode system allows multiple DOS memory
partitions that are 1M byte in length to co exist in the
memory system.
⚫ VM is used to simulate DOS in the modern Windows
Environment
⚫ AC, (alignment check) flag bit activates if a word or
doubleword is addressed on a non-word or non-
doubleword boundary.
⚫ VIF is a copy of the interrupt flag bit available to the
Pentium 4–(virtual interrupt)
⚫ VIP (virtual) provides information about a virtual
mode interrupt for (interrupt pending) Pentium.
⚫ used in multitasking environments to provide virtual
interrupt flags
⚫ ID (identification) flag indicates that the
Pentium microprocessors support the CPUID
instruction.
⚫ CPUID instruction provides the system with
information about the Pentium microprocessor
⚫ Such as its version number and manufacturer
BC
DE
⚫Can be added and represented as
⚫1011 1100
⚫1101 1110
1 1001 1010 (when added)
⚫Sign Flag is affected as Most significant
bit is 1
⚫Zero Flag is not affected as z=0
⚫Parity flag is set if even parity 1111 (4
No’s)
⚫Carry Flag = 1
⚫Auxiliary Carry = 1
⚫ Discuss the Conditional Flag Registers of
8086.Consider the following operation as an
example to mention the status of each flag.

⚫ 21BC
⚫ + 32DE
⚫ Status of each flag after the addition
⚫ 21BC
⚫ 32DE
⚫-
⚫ 0010 0001 1011 1100
⚫ 0011 0010 1101 1110
⚫ 0101 0100 1001 1010
⚫
⚫ CF=0, ZF=0,SF=0, PF=0,ACF=1, ZF=0
⚫
Segment Registers
⚫ Generate memory addresses when combined with
other registers in the microprocessor.
⚫ Four or six segment registers in various versions of the
microprocessor.
⚫ A segment register functions differently in real mode
than in protected mode.
⚫ Following is a list of each segment register, along with
its function in the system.
⚫ CS (code) segment

⚫ The Code segment is a section of memory that

holds the code(program and procedures) used by
the microprocessor.
⚫ The code segment register defines the starting
address of the section of memory holding code
⚫ The code segment is limited to 64K bytes in the
8088-80286 and 4G Bytes in 80386.
⚫ In the 64-bit mode, the code segment register is
still used in the flat model.

.
⚫ DS (data) contains most data used by a program.
⚫ Data are accessed by an offset address or contents of
other registers that hold the offset address
⚫ ES (extra) an additional data segment used by some
instructions to hold destination data
⚫ SS (stack) defines the area of memory used for the
stack.
⚫ stack entry point is determined by the stack segment
and stack pointer registers
⚫ the BP register also addresses data within
the stack segment
⚫ FS and GS segments are supplemental segment
registers available in 80386–Core2 microprocessors.
⚫ allow two additional memory segments for
access by programs
⚫ Windows uses these segments for internal
operations, but no definition of their usage
is available.
2–2 REAL MODE MEMORY ADDRESSING
⚫ Only 8086/88 operate in real mode. The 80286
and above operate in either the real or
protected mode.
⚫ Real mode operation allows addressing of only
the first 1M byte of memory space
⚫the first 1M byte of memory is called the
real memory, conventional memory, or
DOS memory system
Segments and Offsets
⚫ All real mode memory addresses must consist of a
segment address plus an offset address.
⚫ segment address defines the beginning address of
any 64K-byte memory segment
⚫ offset address selects any location within the
64K byte memory segment
⚫ Figure 2–3 shows how the segment plus offset
addressing scheme selects a memory location.
Figure 2–3 The real mode memory-addressing scheme, using a
segment address plus an offset.
– this shows a memory segment
beginning at 10000H, ending at
location IFFFFH
•64K bytes in length

– also shows how an offset address,

called a displacement, of F000H
selects location
1F000H in the memory
⚫ In real mode each segment register is internally appended
with 0H on its rightmost end.
⚫ This forms 20-bit memory address to access a location
within first 1M byte of memory.
⚫ Once the beginning address is known, the ending address is
found by adding FFFFH.
⚫ Segment register contains 3000H , the first address of the
segment is 30000H and last address is 30000H+FFFFH 0r
3FFFFH
⚫ The offset address is always added to the segment starting
address to locate the data.
Default Segment and Offset Registers
⚫ The microprocessor has rules that apply to
segments whenever memory is addressed.
⚫ these define the segment and offset register
combination
⚫ The code segment register defines the start of the
code segment.
⚫ The instruction pointer locates the next instruction
within the code segment
⚫ If CS= 1400H and IP/EIP=1200H, the microprocessor
fetches its next instruction from memory location
14000H+1200H or 15200H
⚫ Another of the default combinations is the
stack.
⚫stack data are referenced through the
stack segment at the memory location
addressed by either the stack pointer
(SP/ESP) or the pointer (BP/EBP)
⚫ Figure 2–4 shows a system that contains four
memory segments.
⚫a memory segment can touch or overlap if
64K bytes of memory are not required for
a segment
⚫ 8086 ASSEMBLY PROGRAM FOR ADDITION OF TWO 8 BIT NUMBERS
⚫ data segment
⚫ a db 09h
⚫ b db 02h
⚫ c dw ?
⚫ data ends
⚫ code segment
⚫ assume cs:code,ds:data
⚫ start:
⚫ mov ax,data
⚫ mov ds,ax
⚫ mov al,a
⚫ mov bl,b
⚫ add al,bl
⚫ mov c,ax
⚫ int 3
⚫ code ends
⚫ end start
TPA
⚫ The transient program area (TPA) holds the DOS
(disk operating system) operating system; other
programs that control the computer system
– a program placed in memory by DOS is loaded
in the TPA at the first available area of memory
above drivers and other TPA programs
– area is indicated by a free-pointer maintained
by DOS
– program loading is handled automatically by
the program loader within DOS
Segment and Offset Addressing Scheme
Allows Relocation
⚫ Segment plus offset addressing allows DOS programs
to be relocated in memory.
⚫ A relocatable program is one that can be placed into
any area of memory and executed without change.
⚫ Relocatable data are data that can be placed in any
area of memory and used without any change to the
program.
⚫ Because memory is addressed within a
segment by an offset address, the memory
segment can be moved to any place in the
memory system without changing any of the
offset addresses.
⚫ Only the contents of the segment register
must be changed to address the program
in the new area of memory.
⚫ Windows programs are written assuming that
the first 2G of memory are available for code
and data.
THANK YOU