Memory Organization

Computer System Architecture

by Morris Mano
&
Computer Organization and Architecture

by William Stallings
 Characteristics
• Location
• Capacity
• Unit of transfer
• Access method
• Performance
• Physical type
• Physical characteristics
• Organisation
 Location
• Internal(CPU registers, main memory, cache)
• External (optical disk, magnetic disks, hard
disk, other usb storage devices)
 Capacity
• Word size
• The natural unit of organisation
• Equal to the no. Of bits used for instruction length.
Number of words
• or no. Of Bytes
• Addressable units N=2A ; A- length of bits
 Unit of Transfer
• Internal
– Usually governed by data bus width(no. Of bits)
• External
– Usually a block which is much larger than a
word(no. Of blocks)
• Addressable unit
– Smallest location which can be uniquely addressed
– Word internally
– Cluster on M$ disks
 Access Methods (1)
• Sequential
– Start at the beginning and read through in order
– Access time depends on location of data and previous location
– A shared R/W mechanism is used.
– e.g. tape
• Direct
– Individual blocks have unique address
– Access is by jumping to vicinity plus sequential search
– Access time depends on location and previous location
– A shared R/W mechanism is used.
– e.g. disk
 Access Methods (2)
• Random
– Individual addresses identify locations exactly
– Access time is independent of location or previous access
– e.g. RAM
• Associative
– Data is located by a comparison with contents of a
portion of the store
– Access time is independent of location or previous access
– e.g. cache
 Memory Hierarchy
• Registers
– In CPU
• Internal or Main memory
– May include one or more levels of cache
– “RAM”
• External memory
– Backing store
Memory Hierarchy - Diagram
 Memory Hierarchy
• The memory unit that directly communicates with CPU
is called the Main Memory.
• Devices that provide backup storage are called
Auxiliary Memory.
• A very high speed memory called Cache is used to
increase the speed of processing by making current
programs and data available to the CPU at a rapid rate.
• CPU logic is faster than main memory access time, so
Cache memory is employed between main memory
and CPU for to match their operation speeds.
•
 Memory Hierarchy
• The reason for 3-level hierarchy is economics.
• As the storage capacity of memory increases, the
cost/bit for storing will decreases and access time
become longer.
• Auxiliary memory and Cache memory are used for
different purposes:
– Cache holds the programs and data that are most
heavily or presently used.
– Auxiliary holds the programs and data that is not in
presently used by CPU.
– CPU has direct access to both.
 Performance
• Access time ( Latency )
– Time between presenting the address and getting
the valid data
• Memory Cycle time
– Time may be required for the memory to
“recover” before next access
– Cycle time is access + recovery
• Transfer Rate
– Rate at which data can be moved
 Transfer Rate

• Rate at which data can be transferred in/out of memory unit.

• For Random Access Memory(=1/cycle time) ,The Following
Relationship holds:

TN= TA + N/R

TN = Average time to read or write N bits.

TA = Average Access Time
N= Numbers Of bits
R = Transfer Rate, in bits per second (bps)
 Physical Types
• Semiconductor
– RAM
• Magnetic
– Disk & Tape
• Optical
– CD & DVD
• Others
– Bubble
– Hologram
Physical Characteristics ( Data Storage )
• Volatility and Non Volatility
( Semiconductor memory )
• Erasable
• Power consumption
 Organisation
• Physical arrangement of bits into words
• Not always obvious
• e.g. interleaved
 Hierarchy List
• Registers
• L1 Cache
• L2 Cache
• Main memory
• Disk cache
• Disk
• Optical
• Tape
 So you want fast?
• It is possible to build a computer which uses
only static RAM
• This would be very fast
• This would need no cache
– How can you cache cache ?
• This would cost a very large amount
 Locality of Reference

Locality of reference.
• During the course of the execution of a
program, memory references tend to cluster.
• e.g. Loops
 Cache
• Small amount of fast memory
• Sits between normal main memory and CPU
• May be located on CPU chip or module
 3 level cache organization
CPU Level 1 level 2 level 3
Main
Cache cache cache memory
Fastest Fast Less
Fast slow

Size increases
 Hit Ratio
• Performance of Cache Memory is measured in
terms of hit ratio.
• When CPU refers to memory and finds the
word in cache , it is said to produce a hit.
• If the word not found in cache, it is main
memory, it is called a miss.
• Hit ratio = no. of hits/(no. of hits+no. of miss)
• Hit ratio verifies the validity of the locality of
reference property.
Cache/Main Memory Structure
 Cache operation – overview
• CPU requests contents of memory location
• Check cache for this data
• If present, get from cache (fast)
• If not present, read required block from main
memory to cache
• Then deliver from cache to CPU
• Cache includes tags to identify which block of
main memory is in each cache slot.
• In this manner, some data are transferred to Cache
so that future references to memory to find the
required words in the Cashe.
Cache Read Operation - Flowchart
 Cache Design
• Size
• Mapping Function
• Replacement Algorithm
• Write Policy
• Block Size
• Number of Caches
 Size does matter
• Cost
– More cache is expensive
• Speed
– More cache is faster (up to a point)
– Checking cache for data takes time
Typical Cache Organization
 Mapping
• The basic characteristic of cache memory is its
fastest time.
• The transformation of data from main
memory is referred to as a mapping process.
• Three types of mapping procedures are used:
1. Direct mapping
2. Associative mapping
3. Set associative mapping
Direct Mapping
 Direct Mapping
Cache Line Table
• The effect of this mapping is that blocks of main memory are
assigned to lines of cache as follows

• Cache line Main Memory blocks held

0 0, m, 2m, 3m…2s-m
1 1,m+1, 2m+1…2s-m+1

m-1 m-1, 2m-1,3m-1…2s-1

 Direct Mapping
Address Structure

Tag s-r Line or Slot r Word w

8 14 2

• 24 bit address
• 2 bit word identifier (4 byte block)
• 22 bit block identifier
– 8 bit tag (=22-14)
– 14 bit slot or line
• No two blocks in the same line have the same Tag field
• Check contents of cache by finding line and checking Tag