‫الجامعة السعودية االلكترونية‬

‫الجامعة السعودية االلكترونية‬

‫‪26/12/2021‬‬
College of Computing and Informatics
OPERATING SYSTEMS
Operating Systems
Module 7

Chapter 9: Main Memory

CONTENTS

 Contiguous Memory Allocation

 Paging

 Structure of the Page Table

 Swapping
WEEKLY LEARNING OUTCOMES

 To provide a detailed description of various ways of

organizing memory hardware

 To evaluate various memory-management techniques

 To understand the concept of Swapping

 INTRODUCTION
Program must be brought (from disk) into memory and placed within a process
for it to be run
Main memory and registers are only storage CPU can access directly
Memory unit only sees a stream of:
addresses + read requests, or
address + data and write requests
Register access is done in one CPU clock (or less)
Main memory can take many cycles, causing a stall
Cache sits between main memory and CPU registers
Protection of memory required to ensure correct operation
 PROTECTION
Need to censure that a process can access only access those addresses in its
address space.
We can provide this protection by using a pair of base and limit registers define
the logical address space of a process
 HARDWARE ADDRESS PROTECTION
CPU must check every memory access generated in user mode to be sure it is
between base and limit for that user

the instructions to loading the base and limit registers are privileged
 MEMORY BINDING
Address binding of instructions and data to memory addresses can happen at
three different stages
Compile time: If memory location known a priori, absolute code can be
generated; must recompile code if starting location changes
Load time: Must generate relocatable code if memory location is not known at
compile time
Execution time: Binding delayed until run time if the process can be moved
during its execution from one memory segment to another
Need hardware support for address maps (e.g., base and limit registers)
PROCESSING OF USER PROGRAM
 ADDRESS SPACE
The concept of a logical address space that is bound to a separate physical
address space is central to proper memory management
Logical address – generated by the CPU; also referred to as virtual address
Physical address – address seen by the memory unit
Logical and physical addresses are the same in compile-time and load-time
address-binding schemes; logical (virtual) and physical addresses differ in
execution-time address-binding scheme
Logical address space is the set of all logical addresses generated by a program
Physical address space is the set of all physical addresses generated by a program
MEMORY MANAGEMENT UNIT (MMU)
Hardware device that at run time maps virtual to physical address
 MEMORY MANAGEMENT UNIT (MMU)
Consider simple scheme. which is a generalization of the base-register scheme.
The base register now called relocation register
The value in the relocation register is added to every address generated by a user
process at the time it is sent to memory
The user program deals with logical addresses; it never sees the real physical
addresses
Execution-time binding occurs when reference is made to location in memory
Logical address bound to physical addresses
 MEMORY MANAGEMENT UNIT (MMU)
Consider simple scheme. which is a generalization of the base-register scheme.
The base register now called relocation register
The value in the relocation register is added to every address generated by a user
process at the time it is sent to memory
CONTIGUOUS ALLOCATION
Main memory must support both OS and user processes
Limited resource, must allocate efficiently
Contiguous allocation is one early method
Main memory usually into two partitions:
Resident operating system, usually held in low memory with interrupt vector
User processes then held in high memory
Each process contained in single contiguous section of memory
 CONTIGUOUS ALLOCATION
Relocation registers used to protect user processes from each other, and from
changing operating-system code and data
Base register contains value of smallest physical address
Limit register contains range of logical addresses – each logical address must be
less than the limit register
MMU maps logical address dynamically
Can then allow actions such as kernel code being transient and kernel changing
size
HARDWARE SUPPORT
VARIABLE PARTITION
Multiple-partition allocation
Degree of multiprogramming limited by number of partitions
Variable-partition sizes for efficiency (sized to a given process’ needs)
Hole – block of available memory; holes of various size are scattered throughout memory
When a process arrives, it is allocated memory from a hole large enough to accommodate it
Process exiting frees its partition, adjacent free partitions combined
Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
 DYNAMIC STORAGE ALLOCATION
First-fit: Allocate the first hole that is big enough
Best-fit: Allocate the smallest hole that is big enough; must search entire list,
unless ordered by size
Produces the smallest leftover hole
Worst-fit: Allocate the largest hole; must also search entire list
Produces the largest leftover hole

First-fit and best-fit better than worst-fit in terms of speed and storage
utilization
 FRAGMENTATION
External Fragmentation – total memory space exists to satisfy a request, but it is
not contiguous
Internal Fragmentation – allocated memory may be slightly larger than
requested memory; this size difference is memory internal to a partition, but
not being used
First fit analysis reveals that given N blocks allocated, 0.5 N blocks lost to
fragmentation
1/3 may be unusable -> 50-percent rule
 ADDRESS SPACE
Reduce external fragmentation by Compaction
Shuffle memory contents to place all free memory together in one large block
Compaction is possible only if relocation is dynamic, and is done at execution time
I/O problem
Latch job in memory while it is involved in I/O
Do I/O only into OS buffers
Now consider that backing store has same fragmentation problems
 PAGING
Physical address space of a process can be noncontiguous; process is allocated physical
memory whenever the latter is available
Avoids external fragmentation
Avoids problem of varying sized memory chunks
Divide physical memory into fixed-sized blocks called frames
Size is power of 2, between 512 bytes and 16 Mbytes
Divide logical memory into blocks of same size called pages
Keep track of all free frames
To run a program of size N pages, need to find N free frames and load program
Set up a page table to translate logical to physical addresses
Backing store likewise split into pages
Still have Internal fragmentation
 ADDRESS TRANSLATION
Address generated by CPU is divided into:
Page number (p) – used as an index into a page table which contains base address
of each page in physical memory
Page offset (d) – combined with base address to define the physical memory
address that is sent to the memory unit

page number page offset

p d
m -n n
For given logical address space 2m and page size 2n
PAGING HARDWARE
PAGING EXAMPLE
PAGING EXAMPLE
PAGING - CALCULATION
Page size = 2,048 bytes
Process size = 72,766 bytes
35 pages + 1,086 bytes
Internal fragmentation of 2,048 - 1,086 = 962 bytes
Worst case fragmentation = 1 frame – 1 byte
On average fragmentation = 1 / 2 frame size
So small frame sizes desirable?
But each page table entry takes memory to track
Page sizes growing over time
FREE FRAMES

Before allocation After allocation

 PAGE TABLE - IMPLEMENTATION
Page table is kept in main memory
Page-table base register (PTBR) points to the page table
Page-table length register (PTLR) indicates size of the page table
In this scheme every data/instruction access requires two memory accesses
One for the page table and one for the data / instruction
The two-memory access problem can be solved by the use of a special fast-lookup
hardware cache called translation look-aside buffers (TLBs) (also called
associative memory).
 TRANSLATION LOOK-ASIDE BUFFER
Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely
identifies each process to provide address-space protection for that process
Otherwise need to flush at every context switch
TLBs typically small (64 to 1,024 entries)
On a TLB miss, value is loaded into the TLB for faster access next time
Replacement policies must be considered
Some entries can be wired down for permanent fast access
ADDRESS SPACE
Associative memory – parallel search

P a ge # F ra m e #

Address translation (p, d)

If p is in associative register, get frame # out
Otherwise get frame # from page table in memory
PAGING HARDWARE WITH TLB
 EFFECTIVE ACCESS TIME
 Hit ratio – percentage of times that a page number is found in the TLB
 An 80% hit ratio means that we find the desired page number in the TLB 80% of the
time.
 Suppose that 10 nanoseconds to access memory.
 If we find the desired page in TLB then a mapped-memory access take 10 ns
 Otherwise we need two memory access so it is 20 ns
 Effective Access Time (EAT)
 EAT = 0.80 x 10 + 0.20 x 20 = 12 nanoseconds
 implying 20% slowdown in access time
 Consider amore realistic hit ratio of 99%,
 EAT = 0.99 x 10 + 0.01 x 20 = 10.1ns
 implying only 1% slowdown in access time.
 MEMORY PROTECTION
Memory protection implemented by associating protection bit with each frame to
indicate if read-only or read-write access is allowed
Can also add more bits to indicate page execute-only, and so on
Valid-invalid bit attached to each entry in the page table:
“valid” indicates that the associated page is in the process’ logical address space,
and is thus a legal page
“invalid” indicates that the page is not in the process’ logical address space
Or use page-table length register (PTLR)
Any violations result in a trap to the kernel
 INVERTED PAGE TABLE
Rather than each process having a page table and keeping track of all
possible logical pages, track all physical pages
One entry for each real page of memory
Entry consists of the virtual address of the page stored in that real memory
location, with information about the process that owns that page
Decreases memory needed to store each page table, but increases time
needed to search the table when a page reference occurs
Use hash table to limit the search to one — or at most a few — page-table
entries
TLB can accelerate access
But how to implement shared memory?
One mapping of a virtual address to the shared physical address
MEMORY PROTECTION
Valid (v) or Invalid (i) Bit In A Page Table
 SWAPPING
A process can be swapped temporarily out of memory to a backing store,
and then brought back into memory for continued execution
Total physical memory space of processes can exceed physical memory
Backing store – fast disk large enough to accommodate copies of all
memory images for all users; must provide direct access to these memory
images
Roll out, roll in – swapping variant used for priority-based scheduling
algorithms; lower-priority process is swapped out so higher-priority process
can be loaded and executed
Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped
System maintains a ready queue of ready-to-run processes which have
memory images on disk
SCHEMATIC VIEW
SWAPPING WITH PAGING
 Main Reference
Chapter 9: Main Memory
(Operating System Concepts by Silberschatz, Abraham, et al. 10th ed.,
ISBN: 978-1-119-32091-3, 2018)
Additional References

Chapter 3.1
Chapter 3.2
Chapter 3.7
(Modern Operating Systems by Andrew S. Tanenbaum and Herbert Bos. 4th
ed., ISBN-10: 0-13-359162-X, ISBN-13: 978-0-13-359162-0, 2015)

sentation is mainly dependent on the textbook: Operating System Concepts by Silberschatz, Abrah
Thank You