CPP110

Prepared MODELING
by : SEQUENTIAL
Dabudz
CIRCUITS IN VERILOG
 PRESENTATION OUTLINE
 Modeling Latches and Flip-Flops

 Blocking versus Non-Blocking Assignments

 Modeling Sequential Circuit Diagrams

 Modeling Mealy and Moore State Diagrams

 Writing Test Benches for Sequential Circuits

 Modeling Registers and Counters

 RECALL: SENSITIVITY
Syntax: LIST OF ALWAYS BLOCK
always @(sensitivity list) begin

procedural statements

end

Sensitivity list is a list of signals: @(signal1, signal2, …)

The sensitivity list triggers the execution of the always block

When there is a change of value in any listed signal

Otherwise, the always block does nothing until another change occurs on a signal
in the sensitivity list
 GUIDELINES FOR
SENSITIVITY LIST
For combinational logic, the sensitivity list must include ALL the signals that are
read inside the always block

Combinational logic can also use: @(*) or @*

For sequential logic, the sensitivity list may not include all the signals that are read
inside the always block

For edge-triggered sequential logic use:

always @(posedge signal1, negedge signal2, …)

The positive edge or negative edge of each signal can be specified in the
sensitivity list
MODELING A D LATCH
WITH ENABLE
// Modeling a D Latch with Enable and output Q
// Output Q must be of type reg
// Notice that the if statement does NOT have else
// If Enable is 0, then value of Q does not change
// The D_latch stores the old value of Q

module D_latch (input D, Enable, output reg Q);

always @(D, Enable)
if (Enable) Q <= D; // Non-blocking assignment
endmodule
MODELING A D-TYPE FLIP-
FLOP
// Modeling a D Flip-Flop with outputs Q and Qbar
module D_FF (input D, Clk, output reg Q, Qbar);
// Q and Qbar change at the positive edge of Clk
// Notice that always is NOT sensitive to D
always @(posedge Clk)
begin
Q <= D; // Non-blocking assignment
Qbar <= ~D; // Non-blocking assignment
end
endmodule
NEGATIVE-EDGE
TRIGGERED D-TYPE FLIP-
FLOP
// Modeling a Negative-Edge Triggered D Flip-Flop
// The only difference is the negative edge of Clk
module D_FF2 (input D, Clk, output reg Q, Qbar);
// Q and Qbar change at the negative edge of Clk
always @(negedge Clk)
begin
Q <= D; // Non-blocking assignment
Qbar <= ~D; // Non-blocking assignment
end
endmodule
 D-TYPE FLIP-FLOP WITH
// Modeling a D Flip-Flop with Synchronous Reset input

SYNCHRONOUS RESET
module D_FF3 (input D, Clk, Reset, output reg Q, Qbar);
// always block is NOT sensitive to Reset or D
// Updates happen only at positive edge of Clk
// Reset is Synchronized with Clk
always @(posedge Clk)
if (Reset)
{Q, Qbar} <= 2'b01;
else
{Q, Qbar} <= {D, ~D};
endmodule
 D-TYPE FLIP-FLOP WITH
ASYNCHRONOUS RESET
// Modeling a D Flip-Flop with Asynchronous Reset input
module D_FF4 (input D, Clk, Reset, output reg Q, Qbar);
// Q and Qbar change at the positive edge of Clk
// Or, at the positive edge of Reset
// Reset is NOT synchronized with Clk
always @(posedge Clk, posedge Reset)
if (Reset)
{Q, Qbar} <= 2'b01;
else
{Q, Qbar} <= {D, ~D};
endmodule
 PROCEDURAL ASSIGNMENT
Procedural assignment is used inside a procedural block only
Two types of procedural assignments:
Blocking assignment:
variable = expression; // = operator
Variable is updated before executing next statement
Similar to an assignment statement in programming languages
Non-Blocking assignment:
variable <= expression; // <= operator
Variable is updated at the end of the procedural block
Does not block the execution of next statements
BLOCKING VERSUS NON-
BLOCKING ASSIGNMENT
Guideline: Use Non-Blocking Assignment for Sequential Logic
q2 q1 q2 q1
in D Q D Q D Q out in D Q out

clk clk
module nonblocking module blocking
(input in, clk, output reg out); (input in, clk, output reg out);
reg q1, q2; reg q1, q2;
always @ (posedge clk) begin always @ (posedge clk) begin
q2 <= in; q2 = in;
q1 <= q2; Read: in, q2, q1 q1 = q2; // q1 = in
out <= q1; out = q1; // out = in
end Parallel Assignment at the end end
endmodule endmodule
 BLOCKING VERSUS NON-
BLOCKING ASSIGNMENT
Guideline: Use Blocking Assignment for Combinational Logic

a a
x x
b b
Old x is
y Old x
c Latched y
c

module blocking module nonblocking

(input a,b,c, output reg x,y); (input a,b,c, output reg x,y);
always @ (a, b, c) begin always @ (a, b, c) begin
x = a & b; // update x x <= a & b; Evaluate all
y = x | c; // y = a&b | c; y <= x | c; expressions
end end Parallel Assignment at the end
endmodule endmodule
 VERILOG CODING
GUIDELINES
1. When modeling combinational logic, use blocking assignments

2. When modeling sequential logic, use non-blocking assignments

3. When modeling both sequential and combinational logic within the same always
block, use non-blocking assignments

4. Do NOT mix blocking with non-blocking assignments in the same always block

5. Do NOT make assignments to the same variable from more than one always block
STRUCTURAL MODELING OF
SEQUENTIAL CIRCUITS
// Mixed Structural and Dataflow
Modeling the Circuit Structure module Seq_Circuit_Structure
(input x, Clock, output y);

wire DA, DB, A, Ab, B, Bb;

// Instantiate two D Flip-Flops

D_FF FFA(DA, Clock, A, Ab);
D_FF FFB(DB, Clock, B, Bb);

// Modeling logic
assign DA = (A & x) | (B & x);
assign DB = Ab & x;
assign y = (A | B) & ~x;

endmodule
 SEQUENTIAL CIRCUIT TEST
BENCH
module Seq_Circuit_TB; // Test Bench
reg x, clk;
wire y;
// Instantiate structural sequential circuit
// Inputs: x and clk
// Output: y
Seq_Circuit_Structure test1 (x, clk, y);
// Generate a clock with period = 10 ns
initial clk = 1;
always #5 clk = ~clk;
// Test sequence: x = 0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 0, . . .
initial begin
x=0; #12 x=1; #10 x=0; #10 x=1; #20 x=0; #10 x=1; #40 x=0;
end
endmodule
SIMULATION WAVEFORMS
Structural and behavioral descriptions have identical waveforms
MODELING A STATE
DIAGRAM
A state diagram can be modeled directly in Verilog

Without the need of having the circuit implementation

An example of a Mealy state diagram is shown below

This is the state diagram of the 111 sequence detector

State assignment: S0 = 00, S1 = 01, and S2 = 10

0/0
0/0 1/1
0/0

reset 00 1/0 01 1/0 10

 MODELING A MEALY STATE
DIAGRAM
module Mealy_111_detector (input x, clock, reset, output z);
reg [1:0] state; // present state
always @(posedge clock, posedge reset)
if (reset) state <= 'b00;
else case(state)
'b00: if (x) state <= 'b01; else state <= 'b00;
'b01: if (x) state <= 'b10; else state <= 'b00;
'b10: if (x) state <= 'b10; else state <= 'b00;
endcase
// output depends on present state and input x
assign z = (state == 'b10) & x;
endmodule

0/0
0/0 1/1
0/0
reset 00 1/0 01 1/0 10
 MODELING A MOORE STATE
DIAGRAM
module Moore_Comparator (input A, B, clk, rst, output GT, LT, EQ);
reg [1:0] state; // present state 00, 11
assign GT = state[1];
assign LT = state[0]; 00
rst
assign EQ = ~(GT | LT); 001
always @(posedge clk, posedge rst)
01 10
if (rst) state <= 'b00;
else case (state)
01
'b00: state <= ({A,B}=='b01)?'b01: 01 10
({A,B}=='b10)?'b10:'b00; 010 100
'b01: state <= ({A,B}=='b10)?'b10:'b01; 10
'b10: state <= ({A,B}=='b01)?'b01:'b10; 00 00
endcase 11 11
01 10
endmodule
 TEST BENCH FOR THE
MOORE COMPARATOR
module Moore_Comparator_TB; // Test Bench
reg A, B, clk, rst;
wire GT, LT, EQ;
Moore_Comparator test (A, B, clk, rst, GT, LT, EQ);
// Reset pulse
initial begin #2 rst = 1; #4 rst = 0; end
// Generate clock
initial clk = 1;
always #5 clk = ~clk;
// Generate input test sequence
initial begin
{A,B}='b00; #12 {A,B}='b11; #10 {A,B}='b01; #10 {A,B}='b11;
#10 {A,B}='b10; #10 {A,B}='b00; #10 {A,B}='b01; #20 {A,B}='b10;
end
endmodule
MOORE COMPARATOR
WAVEFORMS
 MODELING A REGISTER WITH
PARALLEL
module LOAD
Register #(parameter n = 4)
(input [n-1:0] Data_in, input load, clock, reset,
output reg [n-1:0] Data_out);
always @(posedge clock, posedge reset) // Asynchronous
reset
if (reset) Data_out <= 0;
else if (load) Data_out <= Data_in;
endmodule
 MODELING A SHIFT
REGISTER
module Shift_Register #(parameter n = 4)
(input Data_in, clock, reset, output Data_out);
reg [n-1:0] Q;
assign Data_out = Q[0];
always @(posedge clock, negedge reset) // Asynchronous
reset
if (!reset) Q <= 0; // Active Low reset
else Q <= {Data_in, Q[n-1:1]}; // Shifts to the right
endmodule
 MODELING A COUNTER
WITH PARALLEL LOAD
module Counter_with_Load #(parameter n = 4) // n-bit counter
( input [n-1:0] D, input Load, EN, clock,
output reg [n-1:0] Q, output Cout);

assign Cout = (&Q) & EN;

𝐷 3𝐷 2𝐷1𝐷 0
// Sensitive to Positive-edge
𝐿𝑜𝑎𝑑
always @(posedge clock)
if (Load) 𝐶𝑜𝑢𝑡 𝐶𝑜𝑢𝑡 𝐸𝑁 𝐸𝑁
Q <= D; 4-bit Counter
else if (EN) 𝑐𝑙𝑜𝑐𝑘

Q <= Q + 1;

endmodule 𝑄 3𝑄 2𝑄1𝑄 0
 MODELING A GENERIC UP-
DOWN COUNTER
module Up_Down_Counter #(parameter n = 16) // n-bit counter

( input [n-1:0] Data_in,

f=0  Disable counter
input [1:0] f, input reset, clock, f=1  Count up
f=2  Count down
output reg [n-1:0] Count );
f=3  Load counter

// Asynchronous reset Data_in

always @(posedge clock, posedge reset) n

if (reset) Count <= 0; 2

f
Up-Down
else if (f == 1) Count <= Count + 1; reset
Counter
else if (f == 2) Count <= Count – 1; clock
else if (f == 3) Count <= Data_in; n
Count
endmodule
 TEST BENCH FOR THE UP-
DOWN
module COUNTER
Up_Down_Counter_TB; // Test Bench
reg [7:0] Data_in; reg [1:0] f; reg rst, clk; wire [7:0] Count;
// Instantiate an 8-bit test counter
Up_Down_Counter #(8) test (Data_in, f, rst, clk, Count);
// Initialize Data_in (in hexadecimal)
initial Data_in = 8'h2A;
// Generate reset pulse
initial begin #2 rst=1; #4 rst=0; end
// Generate clock
initial clk = 1; always #5 clk = ~clk;
// Generate function sequence
initial begin
#2 f=3; #10 f=1; #30 f=2; #10 f=0; #10 f=1;
end
endmodule
UP-DOWN COUNTER
WAVEFORMS