Chapter 10

Memory Interface
• Two main types of memory – RAM (Read Access memory) and ROM
(Read Only Memory)
• Read-only memory contains system software and permanent system
data.
• RAM contains temporary data and application software.
• Common types of memory-
– ROM (read only memory)
– EEPROM (Flash memory)
– SRAM (static random access memory)
– DRAM (dynamic random access memory)
• Memory pin connections-
– Address inputs
– Data output or input/output
– Selection input (to select the chip)
– Control input (read/write)
• Fig 10.1
• Address Connections
• Address pins are always labeled from A0 (least significant address pin)
to An (n is one less than the number of address pins).
• So if my memory chip has 10 address pins, they will be labeled from A0
to A9.
• Number of address pins are determined by the number of memory
locations inside the memory unit.
• A 1K memory device has 10 address pins(A0 – A9); these 10 address
pins can select any of the 1024 memory locations.
• 4K memory device will have 12 address pins.
• 8K memory device will have 13 address pins and so on.
• 1M memory device will have 20 address pins (A0- A19)
• 400H memory => addresses from 000 – 3FF
• Also 400H is 0100 0000 0000 => 1K-byte memory section.
• So if a memory device has a base address as 10000H and it is a 1K
device, its start location is 10000 and ending location is 10399H.
• 1000H => memory of size 4K.
• Data Connections
• An eight-bit wide memory device is often called a byte-wide memory.
• 1K X 8 memory means memory that is 1K (1024 memory locations) and
the data bus is of size 8 bits.
• Also the size of each memory location is 8 bits.
• 16K X 1 memory means memory that has 16K memory locations and 1
bit memory location and 1 bit data bus.
• Selection Connections
• Chip Select (CS) or chip enable (CE) or simply Select (S)
• These pins are active when they are low.
• If more than one selection pin is there in a chip, all of them must be
enabled to select the chip.
• Control Connections.
• Control input in ROM is Output Enable (OE) or gate (G)
• RAM has either 1 or 2 control pins.
• If only one control input is there, it is R/W. Where 0 represents write
and 1 represents read.
• This pin selects read or write and is able to give data to the data pins
only if the CS is active.
• If RAM has two input pins, they are labeled WE (or W) or OE (or G).
• Both the inputs must not be active at the same moment of time.
• If both the pins are low, data is neither read nor written.
• ROM Memory
• ROM is permanently programmed so that data is always present, even
when the power is disconnected.
• This type of memory is called non-volatile memory.
• EPROM (erasable programmable read only memory) is a type of ROM,
that is most commonly used when software must be changed often.
• EPROM is programmed on a device called EPROM programmer.
• EPROM is also erasable if exposed to high-intensity ultra-violet light for
about 20 mins.
• PROM (programmable read only memory) is also programmed in the
field by burning the fuses; but once it is programmed, it can not be
erased.
• RMM (read mostly memory) , also called flash memory, is EEPROM
(electrically erasable programmable ROM).
• It is also called EAROM (electrically alterable ROM) or NOVRAM (non
volatile RAM)
• These memory devices require more time to erase than a normal RAM.
 2K X 8 EPROM

• Fig 10.2
• PD/ PGM represents power down and program pin.
• If PD/PGM = 0 and CS = 0 => read mode and data is outputted on the
data pins.
• If PD/PGM = 1 and CS = don’t care => power down state, pins remain
as it is.
• If PD/PGM = pulsed from 0 to 1 and CS = 1 => program mode, data is
taken in from the data pins to be written on the EPROM.
• Data appear on the output pins only after a logic 0 is placed on both CE
and OE pins.
• Vpp and Vcc, both are power inputs.
• Memory access time is the time from when the address is placed on the
address bus until the appearance of data on the output pins.
• Basic speed of EPROM is 450ns and microprocessor needs a device
that has access time less than 460ns.
• But these two values are too close, so a wait state has to be inserted, if
EPROM is connected to the microprocessor.

• Read mode timing diagram of EPROM (fig 10-3)

• SRAM (static RAM)
• Static RAM devices retain data as long as power is supplied.
• They are also called volatile memory because they do not retain data
without power supply.
• OE pin is labeled G
• CS pin is S
• WE pin is W

• Timing diagram of SRAM.

 2K X 8 SRAM

• Fig 10.4
• Fig 10.6
• DRAM – Dynamic RAM
• DRAM is same as SRAM, except that it retains data for only 2 or 4 ms
on an integrated capacitor, thus the content of DRAM must be
completely rewritten (refreshed) because the capacitors lose their
charge.
• Another disadvantage of DRAM is that it requires lot of address pins
coz of large size.
• Address pins are also multiplexed in a DRAM.
• When RAS (Row Address Strobe)= 1, the address pins contain A0 – A7
• When RAS = 0, the address pins contain A8 – A15
• CAS (Column Address Strobe) is used to select column address.
• At times, CAS works as chip select input.
• G is output enable pin.
• W is write enable pin.
• Vdd is power supply input
• Vss is ground input
• 10.7
 Figure 10.9

• A0 – A15 and RAS are inputs to the multiplexer from microprocessor.

• A0 – A7 are outputs
• When input to RAS is logic 1 (RAS = 0), B inputs(A8-A15) are connected
to Y outputs of the multiplexer.
• When input to RAS is logic 0 (RAS = 1), A inputs(A0-A7) are connected
to Y outputs of the multiplexer.

• In the following DRAM, there is W/R pin instead of 2 pins, W and G.

• Also pin names are Vcc and GND instead of Vdd and Vss
• 10.10
• Single In-line Memory
Module (SIMM) –
DRAM are organized
on a board to make a
large memory module.
• This is a 30-pin, 4M X 9
SIMM
• 4M = 22 address pins,
though they are
multiplexed, there are
only 11 address pins in
the diagram.
• Here 9th data bit is
parity bit.
• Dual In-line Memory Module (DIMM)
• Pins are placed on both sides of the board.
• The DIMM shown below has 168 pins(1-168), so 1-84 are on one side and 85-168
are on the other side.
• Address Decoding
• EPROM has 11 address pins and the microprocessor has 20, so how
should the remaining 9 pins be connected? This mismatch of number
address pins must be handled carefully.
• When microprocessor has 20 address pins, that implies it needs 1M
memory, but it is connected to a 11pin EPROM, i.e. 2K memory device,
so where is the rest of the memory?
• There is not just one EPROM that is connected to the microprocessor,
there are multiple memory devices that are connected, and which one of
them is chosen is decided on the basis of the remaining address pins of
the microprocessor.
NAND gate Decoder

• 10.13
• 2K X 8 EPROM is used in the figure before, i.e. 11 address pins and 8
data pins.
• The pins A0-A10 of the microprocessor are connected to the address
pins of the EPROM.
• RD output of the microprocessor goes to OE input of the EPROM.
• For CE to be true, inputs A11-A19 should be set to true.
• Also IO/M must be having value 0 for memory mode, thus it is negated
before sending into the NAND gate.
• The address of memory range in this case is
1111 1111 1XXX XXXX XXXX (X represent don’t care)
starting address 1111 1111 1000 0000 0000 – FF800
Ending address 1111 1111 1111 1111 1111 – FFFFF
• 3-to-8 Line Decoder (74LS138) – depending on the value of the 3
selection inputs and 3 enable inputs, the decoder selects one of the 8
outputs.
• The selection pins are named C,B,A and enable pins are named, G1,
G2A, G2B.
• The outputs of the decoder are negated, i.e they are active, when they
are low.
• These output pins are connected to CE pin of a EPROM.
• Thus a decoder selects one of the 8 EPROM’s connected to it.
• The RD signal from 8088 is connected to the OE input of the EPROM.
• What is the complete address range?
• What is the address range of first EPROM?
• What is the address range of third EPROM?
• Each EPROM is 8K X 8, and we have 8 EPROMs, so total memory that
we can access is 64K X 8.
• Fig 10.14
• 2-to-4 line decoder E A B Y0 Y1 Y2 Y3

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

1 X X 1 1 1 1
• Fig 10.17
• In the figure before, U2 is a 128K X 8 SRAM and U3 is an 128K X 8
EPROM.
Address range for SRAM
• To select the SRAM, CE1 must be 0, thus A19 must be 0.
• Also to select the SRAM, output Y0 should be true, i.e. A17 and A18
must both be 0.
• The address range for SRAM is thus 000X XXXX XXXX XXXX XXXX
• SRAM is decoded at location 00000H-1FFFFH.
Address range for EPROM
• Input 1 i.e Vcc is 1.
• M/IO is 0 coz we are dealing with memory device.
• Output at NAND gate 3 is 1.
• Output of NAND gate 6 is used as input to G pin of U1B.
• We want a 0 at the input G, so the input 5 must be equal to 1.
• Thus A19 is 1 to select the EPROM.
• Also A17 and A18 should be 1 coz Y3 is used to select the EPROM.
• Thus the address range for EPROM is 111X XXXX XXXX XXXX XXXX
• EPROM is decoded at locations E0000H-FFFFFH.
• PLD – Programmable Logic Device – works same as a decoder.
• PLD has lot of logic elements, and they are programmable.
• There are 3 SPLD (simple PLD) devices that function the same way but
have different names:
– PLA (programmable logic array)
– PAL (programmable array logic)
– GAL (gated array logic)
• These devices are fuse programmed.

• The PLD in the figure ahead has 10 fixed inputs, 2 fixed outputs, and 6
pins that are programmed as input or output.
8088 / 80188 (8-bit data bus) memory interface
• We have used 3 EPROM blocks of 32K X 8 memory units.
• The 3 EPROM's used here need a memory access time of 450ns, and
8088 needs a memory device of memory access time considerably less
than 460ns.
• Thus in this case we need to insert wait states in the microprocessor.
• A wait state is inserted by adding a logic gate and add another level to
the diagram.
• To insert wait state, we have added a NAND gate, before the output is
fed to the decoder.
• After insertion of the wait state, the microprocessor requires a device
whose memory access time is less than 460 + 200 = 660ns.
• By adding wait state, we have increased the microprocessor read/write
cycle time, and not of the device/ memory.
• And the EPROM we are using takes 450ns (well inside the range)
• What is the address range of U1 , U2, U3
• While calculating the address range, use C,B,A and not A,B,C
• When we reset the system, the execution starts from location FFFF0H.
This location is called cold-start location.
• Fig 10.21
• The address range in the previous figure is 00000H – 7FFFFH
• All the pins that are not used in the previous figure are left for future use.
• 74LS244 and 74LS245 are buffer latches.
• Fig 10-22
Interfacing Flash Memory
• Vpp must be connected to 12V for erase and programming.
• PWD is negated, thus when we want to program the flash memory, this
input must be 0.
• BYTE input selects byte (0) or word(1) mode.
• In byte mode, DQ15 works as A0.
• SRAM can perform a write operation in as little as 10ns, whereas Flash
memory requires approximately 0.4 seconds to erase.
• Flash memory selects locations 1XXX XXXX XXXX XXXX XXXX
• 80000H-FFFFFH
Interfacing 8086, 80186, 80286 and 80386
• 8086, 80186, 80286 and 80386 differ from 8088/80188 in three ways:
– Data bus is 16 bit wide on 8086, it is 8 bit wide on 8088.
– IO/M pin of 8088 is replaced with M/IO pin.
– There is a new control signal called bus high enable (BHE). The pin
A0 or BLE is also used differently.
• The data bus is divided into two separate sections (banks) that are eight
bit wide so that the microprocessor can either write to either half (8-bit)
or both halves(16-bit)
• One bank (low bank) holds all even number addresses and the other
(high bank) holds all odd-numbered addresses.
• Fig 10.25
• Fig 10.26
• Decoder U3 has the BLE pin attached to the pin G2A and decoder U2
has the BHE pin attached to G2A.
• Though a decoder is not activated until its enable pins are selected,
decoder U3 is activated only when 16-bit operation is to be performed or
8-bit low bank is to be accessed.
• Decoder U2 is activated only when 16-bit operation is to be performed or
8-bit high bank is to be accessed.
• Of the decoder U1, we are using only 1 output pin, thus the inputs A20,
A21, A22 are all set to 0.
• To activate the decoder U1, pin A23 is also set to 0.
• Thus the range of locations that this circuit can address is 0000 XXXX
XXXX XXXX XXXX XXXX
• 000000H – 0FFFFFH
• Notice there is no A0 pin.
• Address pin A1 is connected to A0 pin of the memory, A2 is connected
to A1 and so on……
BHE BLE Function

0 0 Both banks enabled

for 16-bit transfer

0 1 High bank enabled for

8-bit transfer

1 0 Low bank enabled for

8-bit transfer

1 1 No bank enabled