Multilevel inverter

By
Nitin H Adroja
Atmiya Institute of Technology & Science, Rajkot
 Introduction of Power Electronics
• It is primarily concerned with application of solid
state devices for conversion and control of electrical
power.
• With the development of power semiconductor
technology, power handling capabilities and switching
speed of the power devices increases tremendously.
• And with the development of digital signal processor,
we can easily achieved smooth control over power
semiconductor switches .
 Introduction of Power Electronics
• Inverter fed AC motor drives is the major
application of power electronics circuits
known as adjustable speed drives (ASD).
• PWM based inverter reduces the amplitudes
of lower order harmonics in the terminal
voltage by shifting the dominating harmonics
towards higher frequencies.
Introduction of Two-level inverter
 Waveform of two-level inverter
• Produce pulsed output
voltage waveform, which
contain a fundamental
component and other
harmonics centre on the
switching frequency and
its multiples.

• Higher switching
frequency leads to better
output voltage and
current waveform,
reduced harmonics
currents and faster
control of drive.
Simulation circuit for Two Level Inverter
Simulation Results for Two Level Inverter
 Disadvantage of Two-level inverter
• Switching losses

• High dV/dt due to high switching frequency

• Electromagnetic interference (EMI)
• Stress on the insulation of the machine windings
• Each devices has to be rated to block entire DC link voltage
during its off time
• Large value of filter is required to get pure sinusoidal
waveform
– So application of two-level inverter is restricted to low and
medium power application.
 Multi-level inverter
• Reduction of disadvantage of two-level inverter
has been made possible by the use of different
class of PWM inverters, termed as Multi-level
Inverter.

“Multi-level inverter are power converters composed

by an array of semiconductor and capacitor voltage
sources, that when properly controlled, can generate
stepped waveform output voltage with adjustable
frequency and amplitude”
 Advantage of Multi-level inverter with
respect to two-level inverter
• It is possible to use power semiconductor devices of lower voltage
ratings to realize high voltage levels at inverter output.
• It is possible to obtained refined output voltage waveform and
reduced total harmonic distortion (THD) in voltage with increased
number of voltage levels (stepped output voltage waveform).
• Inverter can be operated with the lower switching frequency and
hence the switching losses are reduced and also efficiency of
converter has been increased.
• Filter size can be reduced.
• Multilevel converters can draw input current with low distortion.
 Advantage of Multi-level inverter with
respect to two-level inverter
• It is possible to obtain lower dV/dt across power semiconductor devices.
• It is possible to reduce the EMI problems.
• Less stress on the insulation of machine phase windings.
• Multilevel converters produce smaller CM voltage, so It is possible to
obtain machine current with eliminated harmonics, resulting into
reduced torque pulsations in the drive system.

– Unfortunately, multilevel converters do have some disadvantages.

One particular disadvantage is the greater number of power
semiconductor switches needed. Although lower voltage rated
switches can be utilized in a multilevel converter, each switch
requires a related gate drive circuit. This may cause the overall
system to be more expensive and complex.
FFT Analysis
%THD Comparison
 Applications
• High power drives like
– Laminators
– Mills
– Conveyors
– Pumps
– Fans
– Blowers
– Renewable energy source
– Compressors etc….
 Concepts of Multi-level inverter
• Considering that m is the number of steps of
the phase voltage with respect to the
fictitious terminal of the inverter,
– Then the number of steps in the voltage between
two phases of the load is k = 2m + 1.
– And the number of steps in the phase voltage of a
3 phase load in star connection is p = 2k - 1
 Concepts of Multi-level inverter
• The term multilevel starts with the three-level
inverter introduced by Nabae et al.
• By increasing the number of levels in the inverter,
the output voltages have more steps generating a
staircase waveform, which has a reduced
harmonic distortion.
• However, a high number of levels increases the
control complexity and introduces voltage
imbalance problems.
Basic Operating Principle
 Multilevel Inverter Topologies
• Three different major multilevel converter
structures have been applied in industrial
applications:
1. Multilevel Diode Clamped/Neutral Point Inverter,
NPCMLI
2. Multilevel Capacitor Clamped/Flying Capacitor
Inverter, CCMLI
3. Cascaded Multicell Inverter, CMCI
 Multilevel Diode Clamped /
Neutral Point Inverter, NPCMLI
Three Level NPC Inverter

VAZ = Pole Voltage

VAO = Phase Voltage

VAB = Line Voltage

VOZ = Common Mode Voltage

• For an N level (between the phase and the negative
rail) Diode clamped inverter,
– The number of levels in the line-to-line voltage waveform
will be k = 2N-1
– The number of levels in the line to load neutral of a star or
wye load will be p = 2k-1
– The number of capacitors required, independent of the
number of phase, is Ncap = N-1
– While the number of clamping diodes of unequal voltage
rating per phase is Dclamp = 2(N-1) and clamping diode of
equal voltage rating per phase is Dclamp = (N-1)(N-2)
– The number of switches in each leg is Sn = 2(N-1)
– And voltage across each capacitor and switching device is
Vcap = Vdc / (N-1)
 Multilevel Diode Clamped /
Neutral Point Inverter, NPCMLI

Power Switch
(IGBT)
DC Link
Capacitor

DC Source

Clamping
Diode
 Comparison of three-level inverter with
two-level inverter
• Voltage stress on the switches of a three-level
inverter is equal to half to that of a conventional
two-level inverter or equal to voltage across one
capacitor which is Vdc/2.
• Two switches of a pole is always open for any voltage
level and thus share the voltage stress equally.
• Thus voltage rating of the switches is half the DC link
voltage and the blocking voltage rating of the
clamping diode is also half the DC link voltage.
• Diode in the five level configuration has to be rated for
different voltages, which can be higher than the
blocking voltage of the switching devices.
• Blocking voltage of each clamping diode depends on its
position in the structure.
• For n level inverter, voltage across clamping diode is
Vdiode = Vdc (n-1-k) , k = 1,2,…,n-2
(n-1)
• If the blocking rating of each diode is same, than the
number of diode required for each phase is
ND=(n-1)(n-2)
• When n is sufficiently high, the number of diodes makes
the system impractical and implement, which in effect
limits the number of levels.
Switching states of one five-level phase leg
 Explanation
• Diode clamped multi-level inverter is also known as
neutral point clamped because of mid voltage level is
formed by clamping the switching devices to the neutral
point of the DC bus.
• Therefore, the maximum voltage stress on the switch is
limited to the voltage across each capacitor Vdc/(m-1)
which is equal to voltage across each capacitor.
• Half number of switches of a pole is always open for any
voltage level and thus share the voltage stress equally,
thus voltage rating of the switches is equal to voltage
across one capacitor and the blocking voltage rating of
the clamping diode is also equal to voltage across one
 Features
1. High voltage rating for blocking diodes
2. Unequal switching device rating
– S1 conducts only during Van = Vdc/2, whereas switch S4 conducts over the
entire cycle except Van = -Vdc/2.
– Such an unequal conduction duty requires different current rating for
devices.
– Therefore we have to use switches with different current rating.
3. Capacitor voltage unbalance
– Because the voltage levels at the capacitor terminals are different, the
current supplied by the capacitors are also different.
– When inverter operates at unity power factor, the discharge time for
inverter operation for each capacitor is different.
– Such a capacitor charging profile repeats every half cycle, and the result is
unbalanced capacitor voltage between different levels.
– It can be resolved by using controlled constant DC voltage source, PWM
voltage regulators or batteries.
 Advantages
• When the number of levels is high, the
harmonics content is low enough to avoid the
need for filters.
• Inverter efficiency is high because all devices
are switched at the fundamental frequency.
• The control method is simple.
 Disadvantage
• Increase in the number of clamping diodes
leads to a complex bus structure and make the
NPC inverter system impractical to implement
when the number of levels is sufficiently high.
• Capacitor voltage can fluctuate over a
fundamental cycle (depending on the load
current drawn from the DC link) and this
means that devices are subjected block higher
voltages than the ideal condition.
 Multilevel Capacitor Clamped/
Flying Capacitor Inverter, CCMLI
 Multilevel Capacitor Clamped/
Flying Capacitor Inverter, CCMLI

DC Link
Capacitor
Flying Capacitor
or
Floating Capacitor
DC Source
or
Clamping Capacitor

Power Device
(IGBT)
 Switching Table for 3 level FC inverter
State if the Switch
Pole
Voltage
Voltage Effect on flying capacitor voltage
Level S1 S2 S3 S4
Vao

Vdc/2 + 1 1 0 0 No Effect
0 0 1 0 1 0 Charging
0 0 0 1 0 1 Discharging
-Vdc/2 - 0 0 1 1 NO Effect

• S1 and S4, as well as S2 and S3 are two

different complementary pairs of the switch.
Five Level Flying Capacitor Inverter
One leg of Flying Capacitor Inverter
 Switching state for 5 level FC Inverter
State of the switch
Pole
voltage S1 S2 S3 S4 S5 S6 S7 S8
Vdc/ 2 1 1 1 1 0 0 0 0
1 1 1 0 1 0 0 0
Vdc/4 0 1 1 1 0 0 0 1
1 0 1 1 0 0 1 0
0 0 1 0 1 0 1 1
1 1 0 0 1 1 0 0
0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0
0
1 0 0 1 0 1 1 0
0 1 0 1 0 1 0 1
0 1 1 0 1 0 0 1
1 0 0 0 1 1 1 0
- Vdc/4 0 0 0 1 0 1 1 1
0 0 1 0 1 0 1 1
1 1 0 1 0 1 0 0
- Vdc/2 0 0 0 0 1 1 1 1
 Advantage of Redundancy

• As before with the NPCMLI only one switch need to be

opened and one to be closed to change one state to
another. This leads to that the inverter can be modulated at
low (fundamental) switching frequency since a stepped
sinusoidal waveform can be created when every switch is
turned on and off only once per output frequency cycle.
 Explanation
• This circuit is called the flying capacitor
inverter, as independent capacitors clamp the
device voltage to one capacitor voltage level.
• The switches in the pair always be in
complementary states.
 Features
1. Large number of capacitor
– Large number of storage capacitor is required.
– Assuming that voltage across each capacitor is
same as that of a switching device.
– If capacitor with equal voltage rating Vdc/(n-1) as
the main switches are used, and n level inverter
will need ((n-1)(n-2))/2 capacitors per pole as
floating sources in addition to (n-1) main DC bus
capacitor.
 Features
2. Balancing capacitor voltage
– As we already known that, the switching combination for voltage
level except upper and lower one is greater than one.
– Such redundancy of the multi-level configuration is a unique feature
and it is an advantage to maintain the capacitor voltage balance.
– But redundant switching states, vital to capacitor voltage balancing,
are sacrificed to achieve a higher number of output voltage levels.
– To produce same output voltage, the inverter has to switched
different combination so that it easier to manipulate the capacitor
voltage and keep them at their proper value.
– Since the same current flows through all the active capacitors in a
state, energy can be transferred from more charged to less charged
capacitors, balancing the capacitors voltages between the capacitors
that are conducting.
– Thus by proper selection of switching combination , the FC multi-
level inverter may be used in real power conversion.
 Advantage
• Large amount of storage capacitors can
provide capabilities during power outages.
• Provides switch combination redundancy for
balancing different capacitor voltage levels.
• Harmonic content is low enough to avoid the
need of filters.
• Both real and reactive power flow can
controlled.
 Disadvantage
• An excessive number of storage capacitor is
required when the number of levels is high. So
cost of the converter becomes high.
• The inverter control can be very complicated.
• Switching frequency and switching losses are
high for real power transmission.
Cascaded Multi cell Inverter, CMCI
Cascaded Multi cell Inverter, CMCI
 Introduction
• It is a relatively new converter structure, cascaded-
inverters with separate dc sources.
• This new converter can avoid extra clamping diodes or
voltage balancing capacitors.
• To comply with the definition of the previously
mentioned diode-clamp and flying-capacitor multilevel
converters, the “level” in a cascaded-inverters based
converter is defined by m=2s+1, where m is the output
phase voltage level, and s is the number of dc sources.
For example, a 9-level cascaded-inverters based
converter will have four SDC’s and four full bridges.
 Advantage
• Requires the least number of components among all
multilevel converters to achieve the same number of voltage
levels.
• Modularized circuit layout and packaging is possible because
each level has the same structure, and there are no extra
clamping diodes or voltage balancing capacitors.
• Soft-switching can be used in this structure to avoid bulky and
lossy resistor-capacitor-diode snubbers.
• For real power conversions, (ac to dc and dc to ac), the
cascaded-inverter needs separate dc sources. The structure of
separate dc sources is well suited for various renewable
energy sources such as fuel cell, photovoltaic and biomass etc.
 Disadvantage
• Needs separate dc sources for real power
conversions, and thus its applications are
somewhat limited.
 Comparison (For 5 Level)
Topology Diode Clamped Capacitor Clamped Cascaded H Bridge
Output Voltage
N 5 N 5 N 5
Level
Clamping
12 — — — —
Diodes
Clamping
— — 6 — —
Capacitor
DC Link
4 4 2
Capacitor
Main Switches
8 8 8
(With Diode)
Total
24 18 10
Component
 Comparison (For N Level)
1000
900
800
700
600
500 Cascaded
Flying Capacitor
400 Diode Clamped
300
200
100
0
0 5 10 15 20 25 30 35
 Application
• It is used in high power application such as
controlled sources of reactive power.
• Also multi-level inverter reduced the physical size of
the reactive power compensator and makes possible
direct connection to high voltage distribution system,
eliminating distribution transformer and reducing
system cost.
• Also harmonic content of the inverter waveform can
be reduced with appropriate control technique and
thus efficiency of the system can be improved.
1. Reactive power compensation
• With a purely capacitive
load, the inverter operating
as a dc-ac converter can
draw reactive current from
AC supply.
• In this figure, load side is
connected to AC supply and
the DC side is open, means
not connected to any DC
voltage.
• The DC side capacitor acts as
a load.
• When a multilevel converter draws pure reactive power,
the phase voltage and current are 90“ apart. Such a
converter, when serving for reactive power
compensation, is called a static var generator (SVG).
• All the three converters can be used as in reactive power
compensation without having the voltage unbalance
problem.
• The relationship of the source voltage vector, Vs, and the
converter voltage vector, Vc, is simply Vs = Vc + jIcXs,
where Ic is the converter current vector, and Xs is the
impedance of the inductor, Ls.
• The polarity and the magnitude of the reactive current
are controlled by the magnitude of the converter voltage,
Vc, which is a function of the dc bus voltage and the
voltage modulation index.
2. Back-to-Back Intertie
• When interconnecting two diode-clamp
multilevel converters together with a “dc
capacitor link", the left-hand side converter
serves as the rectifier for utility interface, and
the right-hand side converter serves as the
inverter to supply the ac load.
• Each switch remains switching once per
fundamental cycle. The result is a well-balanced
voltage across each capacitor while maintaining
the staircase voltage wave, because the
unbalance capacitor voltages on both sides tend
to compensate each other. Such a dc capacitor
link is categorized as the "back-to-back intertie”.
• The purpose of the back-to-back intertie is to connect
two asynchronous systems. It can be treated as 1) a
frequency changer, 2) a phase shifter, or 3) a power flow
controller. The power flow between two systems can be
controlled bi-directionally.
• Fig. illustrates the phasor diagram for real power
transmission from the source end to the load end. This
diagram indicates that the source current can be leading
or lagging the source voltage. The converter voltage is
phase-shifted from the source voltage with a power
angle, α. If the source voltage is constant, then the
current or power flow will be controlled by the converter
voltage. For α = 0, the current is either 90⁰ leading or
lagging, meaning that only reactive power is generated.
3. Utility Compatible Adjustable Speed Drives

• An ideal utility compatible system requires unity power factor,

negligible harmonics, no EMI, and high efficiency.
• By extending the application of the back-to-back intertie the
multilevel converter can be used for a utility compatible
adjustable speed drive (ASD) with the input from the utility
constant frequency ac source and the output to the variable
frequency ac load.
• The major differences, when using the same structure for ASD's
and for back-to-back interties, are the control design and the
size of the capacitor. Because the ASD needs to operate at
different frequencies, the dc link capacitor needs to be well-
sized to avoid a large voltage swing under dynamic conditions.
Switching Device Current in 5 level inverter
circuit
• If we assume that, load inductance is
sufficiently high and capacitor maintain their
voltage so that the output current is sinusoidal
in nature, and is given by

• In 5 level inverter, the most inner switches

such as S4 and S1’ carry more current than the
most outer switches S1 and S4’.
• Each input node current can be expressed as a
function of switching function SFn as given by
• The output load current is given by

and the rms value of each current is

where In(rms) is the rms current of the nth node

• For balanced switching , we get

Capacitor Voltage Balancing
 Capacitor Voltage Balancing
• Thus, the average value of input node current i1, I1(avg) is given by

• Similary, the average value of i2, I2(avg) is given by

• By symmetry, I3(avg) = 0, I4(avg) = - I2(avg) and I5(avg) = - I1(avg)

• Therefore, if each capacitor voltage is to be under regulation, the average
currents per cycle which should be supplied from each capacitor are as
follows:

• So

• Obviously, Ic1(avg) < Ic2(avg) for α1 < α2