UNIT-4 Memory

Memory Hierarchy
• The memory unit that communicates directly with the CPU is called the main
memory. The principal technology used for the main memory is based on
semiconductor integrated circuits. Integrated circuit RAM chips are available in
two possible operating modes, static and dynamic.
• Static RAM: The static RAM consists essentially of internal flip-flops that store
the binary information. The stored information remains valid as long as power
is applied to the unit.
• Dynamic RAM: The dynamic RAM stores the binary information in the form of
electric charges that are applied to capacitors. The stored charge on the
capacitors tends to discharge with time and
• the capacitors must be periodically recharged by refreshing the dynamic
memory.
• Most of the main memory in a general-purpose computer is made up of RAM
• integrated circuit chips, but a portion of the memory may be constructed with
• ROM chips.
• The ROM portion of main memory is needed
for storing an initial program called a
bootstrap loader. The bootstrap loader is a
program whose function is to start the
computer software operating when power is
turned on.
• Since RAM is volatile, its contents are
destroyed when power is turned off. The
contents of ROM remain unchanged after
power is turned off and on again.
Memory Hierarchy
RAM Chips
• However, since a ROM can only read, the
data bus can only be in an output mode. For
the same-size chip, it is possible to have
more bits of ROM than of RAM, because the
internal binary cells in ROM occupy less
space than in RAM. For this reason, the
diagram specifies a 512-byte ROM, while the
RAM has only 128 bytes.
ROM Chips
 Memory Address Map

• The interconnection between memory and

processor is established from knowledge of the
size of memory needed and the type of RAM
and ROM chips available. The addressing of
memory can be established by means of a table
that specifies the memory address assigned to
each chip. The table, called a memory address
map, is a pictorial representation of assigned
address space for each chip in the system.
To demonstrate with a particular example, assume that a computer system
needs 512 bytes of RAM and 512 bytes of ROM.
 Associative Memory or Content
Addressable Memory(CAM)
• The time required to find an item stored in memory
can be reduced if stored data can be identified for
access by the content of the data itself rather than
by an address.
• A memory unit accessed by content is called an
associative memory or content addressable
memory (CAM).
• This type of memory is accessed simultaneously
and in parallel on the basis of data content rather
than by specific address or location.
 CAM
• When a word is written in an associative memory, no address is
given. The memory is capable of finding an empty unused location
to store the word. When a word is to be read from an associative
memory, the content of the word, or part of the word, is specified.
The memory locates all words which match the specified content
and marks them for reading.
• Because of its organization, the associative memory is uniquely
suited to do parallel searches by data association. Moreover,
searches can be done on an entire word or on a specific field within
a word.
• An associative memory is more expensive than a random access
memory because each cell must have storage capability as well as
logic circuits for matching its content with an external argument.
 Cache Mapping Techniques
• The performance of cache memory is frequently
measured in terms of a quantity called hit ratio.
• When the CPU refers to memory and finds the
word in cache, it is said to produce a hit . If the
word is not found in cache, it is in main memory
and it counts as a miss .
• The ratio of the number of hits divided by the
total CPU references to memory (hits plus
misses) is the hit ratio.
• Three types of mapping procedures are:
1. Associative mapping
2. Direct mapping
3. Set-associative mapping
• The main memory can store 32K words of 12 bits
each. The cache is capable of storing 512 of these
words at any given time. The CPU communicates
with both memories. It first sends a 15-bit address
to cache. If there is a hit, the CPU accepts the 12-bit
data from cache. If there is a miss, the CPU reads
the word from main memory and the word is then
transferred to cache.
 Associative Mapping
• The fastest and most flexible cache
organization uses an associative memory. The
associative memory stores both the address
and content (data) of the memory word. This
permits any location in cache to store any
word from main memory.
 Associative Mapping
• The address value of 15 bits is shown as a five-digit octal number and its
corresponding 12 -bit word is shown as a four-digit octal number. A CPU
address of 15 bits is placed in the argument register and the associative
memory is searched for a matching address. If the address is found, the
corresponding 12-bit data is read and sent to the CPU.
• If no match occurs, the main memory is accessed for the word. The
address-data pair is then transferred to the associative cache memory.
• If the cache is full, an address-data pair must be displaced to make room
for a pair that is needed and not presently in the cache.
• The decision as to what pair is replaced is determined from the
replacement algorithm that the designer chooses for the cache.
• Ex. FIFO, LRU, OPTIMAL etc.
• Associative memories are expensive compared to random-access
memories because of the added logic associated with each cell.
 Direct Mapping
• Associative memories are expensive compared
to random-access memories because of the
added logic associated with each cell. The
possibility of using a random-access memory
for the cache is investigated
• The CPU address of 15 bits is divided into two
fields. The nine least significant bits constitute
the index field and the remaining six bits form
the tag field.
 Direct Mapping with Block Size of 8
words
• The block number is specified with a 6-bit field and
the word within the block is specified with a 3- bit
field.
• The tag field stored within the cache is common to
all eight words of the same block. Every time a miss
occurs, an entire block of eight words must be
transferred from main memory to cache memory.
• Although this takes extra time, the hit ratio will most
likely improve with a larger block size because of the
sequential nature of computer programs.
 Set-Associative Mapping
• The disadvantage of direct mapping is that two words
with the same index in their address but with different tag
values cannot reside in cache memory at the same time.
• A third type of cache organization, called set associative
mapping, is an improvement over the direct mapping
organization in that each word of cache can store two or
more words of memory under the same index address.
• Each data word is stored together with its tag and the
number of tag-data items in one word of cache is said to
form a set.
2- Way Set-associative Cache mapping
 2- Way Set-associative Cache mapping

• Each index address refers to two data words and their

associated tags. Each tag requires six bits and each data
word has 12 bits, so the word length is 2(6 + 12) = 36
bits.

• An index address of nine bits can accommodate 512

words. Thus the size of cache memory is 512 x 36. It can
accommodate 1024 words of main memory since each
word of cache contains two data words. In general, a
set-associative cache of set size k will accommodate k
words of main memory in each word of cache.
 2- Way Set-associative Cache mapping
• The words stored at addresses 01000 and 02000 of main memory are
stored in cache memory at index address 000. Similarly, the words at
addresses 02777 and 00777 are stored in cache at index address 777.
• When the CPU generates a memory request, the index value of the
address is used to access the cache. The tag field of the CPU address
is then compared with both tags in the cache to determine if a match
occurs. The comparison logic is done by an associative search of the
tags in the set similar to an associative memory search: thus the
name "set-associative."
• The hit ratio will improve as the set size increases because more
words with the same index but different tags can reside in cache.
However, an increase in the set size increases the number of bits in
words of cache and requires more complex comparison logic.
 2- Way Set-associative Cache mapping

• When a miss occurs in a set-associative cache

and the set is full, it is necessary to replace
one of the tag-data items with a new value.
The most common replacement algorithms
used are: random replacement, first-in, first-
out (FIFO), and least recently used (LRU).
 Writing into Cache
• When the CPU finds a word in cache during a
read operation, the main memory is not
involved in the transfer. However, if the
operation is a write, there are two ways that
the system can proceed.
• Write Through
• Write Back
 Write-Through
• The simplest and most commonly used
procedure is to update main memory with
every memory write operation, with cache
memory being updated in parallel if it contains
the word at the specified address. This is
called the write-through method. This method
has the advantage that main memory always
contains the same data as the cache.
 Write-Back
• The second procedure is called the write-back method. In
this method only the cache location is updated during a write
operation. The location is then marked by a flag so that later
when the word is removed from the cache it is copied into
main memory. The reason for the write-back method is that
during the time a word resides in the cache, it may be
updated several times; however, as long as the word remains
in the cache, it does not matter whether the copy in main
memory is out of date, since requests from the word are
filled from the cache. It is only when the word is displaced
from the cache that an accurate copy need be rewritten into
main memory.
 Virtual Memory
• In a memory hierarchy system, programs and data are first stored in auxiliary
memory. Portions of a program or data are brought into main memory as they
are needed by the
CPU.
• Virtual memory is a concept used in some large computer systems that permit
the user to construct programs as though a large memory space were available,
equal to the totality of auxiliary memory. Each address that is referenced by the
CPU goes through an address mapping from the so-called virtual address to a
physical address in main memory.
• Virtual memory is used to give programmers the illusion that they have a very
large memory at their disposal, even though the computer actually has a
relatively small main memory. A virtual memory system provides a mechanism
for translating program generated addresses into correct main memory
locations.
• The translation or mapping is handled automatically by the hardware by means
of a mapping table.
Address Space and Memory Space
• An address used by a programmer will be called a
virtual address, and the set of such addresses the
address space.
• An address in main memory is called a location or
physical address. The set of such locations is
called the memory space. In most computers the
address and memory spaces are identical. The
address space is allowed to be larger than the
memory space in computers with virtual memory.
• Consider a computer with a main-memory capacity of 32K words (K = 1024).
Fifteen bits are needed to specify a physical address in memory since 32K =
2^15. Suppose that the computer has available auxiliary memory for storing
2^20 = 1024K words. Thus auxiliary memory has a capacity for storing
information equivalent to the capacity of 32 main memories. Denoting the
address space by N and the memory space by M, we then have for this example
N = 1024K and M = 32K.
• In a multi-program computer system, programs and data are transferred to and
from auxiliary memory and main memory based on demands imposed by the
CPU. Suppose that program 1 is currently being executed in the CPU. Program 1
and a portion of its associated data are moved from auxiliary memory into
main memory as shown in Fig. 12-16. Portions of programs and data need not
be in contiguous locations in memory since information is being moved in and
out, and empty spaces may be available in scattered locations in memory. In
our example, the address field of an instruction code will consist of 20 bits but
physical memory addresses must be specified with only 15 bits.
• A table is then needed, as shown in Fig. , to map a virtual address of 20 bits to
a physical address of 15 bits. The mapping is a dynamic operation, which
means that every address is translated immediately as a word is referenced
by CPU.
• Consider a computer with an address space of
8K and a memory space of 4K. If we split each
into groups of 1K words we obtain eight pages
and four blocks. At any given time, up to four
pages of address space may reside in main
memory in any one of the four blocks.
• Note that the line address in address space
and memory space is the same; the only
mapping required is from a page number to a
block number.
Question: An address space is specified by 24
bits and the corresponding memory space by
16 bits.
a. How many words are there in the address
space?
b. How many words are there in the memory
space?
c. If a page consists of 2K words, how many
pages and blocks are there in the system?
2D Memory
2.5 D MEMORY
Cache Performance