Chapter 8: Main Memory

Operating System Concepts – 9th Edition Silberschatz, Galvin &Gagne ©2013

 Chapter 8: Memory Management
 Background
 Swapping
 Contiguous Memory Allocation
 Segmentation
 Paging
 Structure of the Page Table (Out of Syllabus)
 Example: The Intel 32 &64-bit Architectures (Out of
Syllabus)
 Example: ARM Architecture (Out of Syllabus)

Operating System Concepts – 9th Edition 8.2 Silberschatz, Galvin &Gagne ©2013
 Objectives
 To provide a detailed description of various ways of
organizing memory hardware.

 To discuss various memory-management techniques,

including paging & segmentation.

 To provide a detailed description of the Intel Pentium,

which supports both pure segmentation & segmentation
with paging.

Operating System Concepts – 9th Edition 8.3 Silberschatz, Galvin &Gagne ©2013
 Background
 Memory is central to the operation of a modern computer
system.
 Memory consists of a large array of bytes, each with its own
address.
 The CPU fetches instructions from memory according to the
value of the program counter.

 These instructions may cause additional loading from & storing

to specific addresses.

 A typical instruction-execution cycle, for example,

 First fetches an instruction from memory.
 The instruction is then decoded & may cause operands to be
fetched from memory. - the data to be operated on
(constant, variable, value returned by a function, etc.)
 After the instruction has been executed on the operands.
 Results may be stored back in memory.
Operating System Concepts – 9th Edition 8.4 Silberschatz, Galvin &Gagne ©2013
 Background
 A set of data entries indexed by
addresses.

 Typically, the basic data unit is byte.

 In 32-bit machines, 4 bytes grouped to

words.

 The addresses used by the RAM chips

are called physical addresses.

Operating System Concepts – 9th Edition 8.5 Silberschatz, Galvin &Gagne ©2013
 Basic Hardware
 The general-purpose storage that the CPU access
directly are
 Main memory
 Registers built into the processors

 Any instructions in execution & any data being used

by the instructions must be in one of these direct
access storage devices.

 If the data are not in memory, they must be moved

there before the CPU can operate on them.

 Registers that are built into the CPU are generally

accessible within one cycle of the CPU clock.
 Perform simple operations at the rate of one or
more operations per clock tick.
Operating System Concepts – 9th Edition 8.6 Silberschatz, Galvin &Gagne ©2013
 Basic Hardware
 Main memory, accessed via a transaction on the memory
bus.
 Memory bus connects all the internal components of a
computer, such as CPU and memory, to the motherboard.

 Completing a memory access may take many cycles of the

CPU clock.

 In such cases, the processor normally needs to stall, since

it does
not have the data required to complete the instruction that
it is executing.
OperatingSystem Concepts – 9th Edition 8.7 Silberschatz, Galvin &Gagne ©2013
 Basic Hardware
 The remedy is to add fast memory between the CPU & main
memory.

 on the CPU chip for fast access, we have cache.

 To manage a cache built into the CPU, the hardware

automatically
speeds up memory access without any OS control.

 Not only are we concerned with the relative speed of accessing

physical memory, but we also must ensure correct operation.

 For proper system operation we must protect the OS from

access by user processes.

 On multiuser systems, we must additionally protect user

processes from
one another.

 This protection must be provided by the hardware.

Operating System Concepts – 9th Edition 8.8 Silberschatz, Galvin &Gagne ©2013
 Basic Hardware
 We need to make sure that each process has a separate memory
space.

 Separate per-process memory space protects the processes from

each other.

 It is fundamental to having multiple processes loaded in memory

for concurrent execution.

 To separate memory spaces, we need the ability to determine the

range of legal addresses that the process may access.

 And ensure that the process can access only these legal
addresses.

 Protection by using two registers: a base register & a limit register.

 Base register holds the smallest legal physical memory

address.

 Limit register specifies the size of the range.

Operating System Concepts – 9th Edition 8.9 Silberschatz, Galvin &Gagne ©2013
 Basic Hardware

Main memory & registers are only storage CPU can access
directly.

Register access in one CPU clock (or less)

Cache sits between main memory & CPU registers.

Protection of memory required to ensure correct operation.

Operating System Concepts – 9th Edition 8.10 Silberschatz, Galvin &Gagne ©2013
 Base & Limit Registers
 A pair of base & limit registers define the logical address space.

 CPU must check every memory access generated in user mode

to be sure it is
between base & limit for that user.

 If the base register holds 300040 &

 the limit register is 120900, then the program
 Can legally access all addresses from 300040
through 420939 (inclusive).

 300040 + 120900 = 420940

• The base register holds the lowest
address allocated to a process. (starting
address).

• The limit register specifies the size of

range.
• Base register = 1400
• Limit register = 1000
program can legally access all addresses from 1400 through 2400
(inclusive).
Operating System Concepts – 9th Edition 8.11 Silberschatz, Galvin &Gagne ©2013
 Hardware Address Protection
• Using the values in the base & limit
registers, CPU checks every address generated in user mode.

• Any attempt in user mode to access memory out of bounds

results in a trap.

• Prevents a user program from accidently or deliberately

modifying the code or data structures of either the OS or other
users.

Operating System Concepts – 9th Edition 8.12 Silberschatz, Galvin &Gagne ©2013
 Address Binding
 A program resides on a disk as binary executable file.

 To be executed the program must be brought into memory.

 Depending on the memory management in use, the process

may be
moved between disk & memory during its execution.

 The processes on the disk that are waiting to be brought

into memory for
execution form the input queue- contains many
processes.

 The normal single-tasking procedure is to select one of the

processes in
the input queue & to load that process into memory.

Operating System Concepts – 9th Edition 8.13 Silberschatz, Galvin &Gagne ©2013
 Address Binding

Without support, a user

process must be loaded
into address 0000

But this is inconvenient to

have first user process
physical address always at
0000

So How can it be?

Addresses represented in
different ways at different
stages of a program’s life.

Operating System Concepts – 9th Edition 8.14 Silberschatz, Galvin &Gagne ©2013
 Address Binding
 Addresses binding of instructions and data to memory addresses can
happen at
three different stages:

 Source program are generally symbolic (variable, functions classes,

etc.).
 You never know the addresses of the instructions. We use variable
names not addresses. The assembler maps them to relative
addresses (offset of the starting).

 Compiler typically binds these symbolic addresses to relocatable

addresses
 If a program starts at 00000 we can say the instruction is located
“14 bytes from the beginning of this program.
 Why this is needed?
 Because when you run the program, it is loaded into memory.
 It does not know where is this instruction in memory but it will
refer to the start of the program.

 The linkage editor or loader binds the relocatable addresses to absolute

addresses (74014).

 The actual program can be loaded into memory location 74014.

Operating System Concepts – 9th Edition 8.15 Silberschatz, Galvin &Gagne ©2013
 Address Binding
 Each binding is a mapping from one address space to another.

 The conversion from variable names to relocatable addresses is

called address
binding.

 This conversion of relocatable to physical address is called

address binding.

 This binding works for instructions & data to memory addresses.

 Can be done at any step along the way.

 It can happen at different times.

Operating System Concepts – 9th Edition 8.16 Silberschatz, Galvin &Gagne ©2013
 Binding of Instructions & Data to Memory
 Address binding of instructions & data to memory addresses can
happen at
three different stages:

 Compile time:
 If the compiler is responsible for binding, then it is called
compile-time binding.

 The compiler translates symbolic addresses to absolute

addresses at the time of compilation.

 Before loading program into memory.

 The compiler interact with the OS to perform compile time
address binding.

 If it is known where the program will reside in memory, then

absolute code can be generated. This is rarely possible.

 It does not work like this - we do not know the address at

compile time.
Operating System Concepts – 9th Edition 8.17 Silberschatz, Galvin &Gagne ©2013
 Binding of Instructions &Data to Memory
 Load time:

 The binding will be done after loading the program inro

memory.

• The binding will be done by the loader (os memory manager).

 If it is not known at compile time where the process will

reside in memory, then the compiler must generate
relocatable code (address relative to the start of the
program.

 Generate code with respect to a starting position – program

can be anywhere.

Operating System Concepts – 9th Edition 8.18 Silberschatz, Galvin &Gagne ©2013
 Binding of Instructions &Data to Memory
 Execution time:
 If memory location is not known in the previous stages, then
binding delayed until run time.
 If the process can be moved during its execution from one
memory segment to another, then binding delayed.

 Execution time address binding is done by processor.

 It generates physical address. It generates dynamic absolute
address.

 The program can move from one location to another in memory

when it is executed therefore:

 We need special hardware to support this address mapping.

 That is done by using the base & limit registers.

 Most popular and flexible scheme, providing we have the

requisite hardware
Operating System Concepts – 9th Edition 8.19 Silberschatz, Galvin &Gagne ©2013
 Multistep Processing of a User Program

If the address is
known use absolute

Relocatable code binding

address

Absolute address
generated by hardware

Operating System Concepts – 9th Edition 8.20 Silberschatz, Galvin &Gagne ©2013
 Logical vs. Physical Address Space
 The concept of a logical address space that is bound to a separate
physical address space is central to proper memory management.
 Logical address
 Generated by the CPU - also referred to as virtual address.
 CPU will execute instruction so it will send the address to
memory.
 Memory will convert it into a physical address.
 Logical address is different for each process.
 The starting is 0 the ending is the limit of the process.
 Logical address is used as a reference to access the physical
memory location by CPU.
 Physical address
 Refers to an actual physical location located in the memory unit.
 Address seen by the memory unit.

 Logical address space is the set of all logical addresses generated

by a program.

 Physical Address Space is used for all physical addresses

corresponding to the logical addresses in a Logical address space.

Operating System Concepts – 9th Edition 8.21 Silberschatz, Galvin &Gagne ©2013
 Logical vs. Physical Address Space
Terms logical address physical address
Definitio The CPU generates the logical The physical address is a
n address while the program is location in memory.
running. Actual address of data in
Virtual address because it does memory.
not exist physically.
Location The logical address does not The physical address is a
exist physically in the memory, location in the memory
and therefore it is sometimes unit.
known as a virtual address.
Access The logical address is used as a The physical address
reference to access the physical cannot be accessed
address. directly.
User The user can use the logical Never deals with physical
address to access the physical addresses.
address.
Address The set of all the logical The set of all physical
space addresses generated by the CPU addresses corresponding
is called to the logical addresses in
logical address space. the logical address space
Operating System Concepts – 9th Edition 8.22 Silberschatz, Galvin &Gagne ©2013
 Memory-Management Unit (MMU)
 A memory management unit (MMU) is a
computer hardware component.

 MMU is the computer hardware that is responsible for managing

the
computer’s memory system.

 It's usually integrated into the processor, although, in some

systems, it
occupies a separate integrated circuit (IC).

 The memory management unit performs three major functions:

 Hardware memory management- Deals with system RAM and Cache memory.
 Operating system memory management- ensures adequate memory resources
are available for the objects and data structures of each running program.
 Application memory management- allocates and optimize memory among
applications.

 .
Operating System Concepts – 9th Edition 8.23 Silberschatz, Galvin &Gagne ©2013
 Memory-Management Unit (MMU)

What does an MMU do?

 Handles all memory & caching operations associated

with the processor.

 MMU is responsible for all aspects of memory

management.

 MMU is used to map logical addresses to physical

addresses.

 There are many methods for mapping logical addresses

to physical addresses.

Operating System Concepts – 9th Edition 8.24 Silberschatz, Galvin &Gagne ©2013
 Memory-Management Unit (MMU)
 To start, consider simple scheme where the value in the
relocation register is added to every address generated by
a user process at the time it is sent to memory.

 Base register now called relocation register.

 MS-DOS on Intel 80x86 used 4 relocation registers.

 The user program deals with logical addresses.

 It never sees the real physical addresses.
 In execution-time binding occurs when reference is
made to location in memory.
 Logical address bound to physical addresses

Operating System Concepts – 9th Edition 8.25 Silberschatz, Galvin &Gagne ©2013
 Dynamic relocation using a relocation register
 Routine is not loaded until it is
called. Base Register
Relocation Register
 Better memory-space utilization-
unused routine is never loaded.

 Useful when large amounts of code

are needed to handle infrequently
occurring cases.

 Mapping from Logical to physical is

done by the hardware MMU.

 No special support from the OS is

required
 Implemented through program
design.
• CPU generates
OS can help byaproviding
logical address 346.
libraries to
• Then it is added to relocation
implement dynamic loading. register 14000.
• An access to location 346 is mapped to location 14346.
• User program only sees 346.
Operating System Concepts – 9th Edition 8.26 Silberschatz, Galvin &Gagne ©2013
 Dynamic Linking
 Some OS support only static linking.

 Static linking – system libraries & program code combined

by the loader into the binary program image.

 This is used with system libraries such as language

subroutine libraries.

 Each program on a system must include a copy of its

language library in the executable image.

 This waste both disk space & memory.

Operating System Concepts – 9th Edition 8.27 Silberschatz, Galvin &Gagne ©2013
 Dynamic Linking
 Dynamic loading

 A routine is not loaded until is called.

 All routines are kept on disk in a relocatable load format.

 The main program is loaded into memory and executed.

 When a routine needs to call another routine the calling

routine first checks to see whether the other routine has
been loaded.

 If it has not, the linking loader is called to load the

routine into memory.

 Update the program’s address tables to reflect this

change.

 The linking is postponed8.28until executionSilberschatz,

time. Galvin &Gagne ©2013
Operating System Concepts – 9th Edition
 Dynamic Linking
Dynamic Linking
With dynamic linking a stub is included in the image for
each library routine reference.

Stub is a small piece of code:

 Used to locate the appropriate memory-resident library
routine.
 Load the library if the routine is not already present.
 Execute the library routine.

When the stub is executed, it checks to see whether the

needed routine is already in memory.
 If it is not, the program loads the routine into memory.
 OS checks if routine is in processes’ memory address
 If not in address space, add to address space.

Operating System Concepts – 9th Edition 8.29 Silberschatz, Galvin &Gagne ©2013
 Dynamic Linking

 Dynamic linking is particularly useful for libraries.

System also known as shared libraries.

 Consider applicability to patching system libraries.

Versioning may be needed.

 The advantages:
 Useful for libraries – shared libraries.
 A routine is loaded only when it is needed.
 It is the responsibility of the users to design their
programs to advantage of such a method.
 Not OS responsibility but OS help in providing library
routines.

Operating System Concepts – 9th Edition 8.30 Silberschatz, Galvin &Gagne ©2013
 Swapping
 A process must be in memory to be executed.

 A process can be swapped temporarily out of memory to a

backing store & then brought back into memory for
continued execution.

 Backing store is part of the hard disk – Extended memory

used by OS.

 Backing store – fast disk, large enough to accommodate

copies of all memory images for all users.

 Why we need swapping?

Totalphysical memory space of processes can exceed

physical memory.

 Must provide direct access to these memory images.

Operating System Concepts – 9th Edition 8.31 Silberschatz, Galvin &Gagne ©2013
 Swapping
 The system maintain a ready queue consisting of
 All process whose memory image on the backing store &
ready to run.

 Whenever the CPU scheduler decides to execute a process, it

calls the
dispatcher.

 The dispatcher checks to see whether the next process in

the queue is in memory.

 If it is not, & if there is no free memory region, the dispatcher

 swaps out a process currently in memory &
 swaps in the desired process.

 It then reloads registers & transfers control to the selected

process.

 The context switch time in swapping system is fairly high.

Operating System Concepts – 9th Edition 8.32 Silberschatz, Galvin &Gagne ©2013
 Schematic View of Swapping

Operating System Concepts – 9th Edition 8.33 Silberschatz, Galvin &Gagne ©2013
 Swapping

Roll out, Roll in – swapping variant used for priority-based

scheduling algorithms.

Lower-priority process is swapped out (rolled out)

Higher-priority process swapped in (rolled in) - loaded &

executed.

Major part of swap time is transfer time.

Total transfer time is directly proportional to the amount of

memory swapped.

Operating System Concepts – 9th Edition 8.34 Silberschatz, Galvin &Gagne ©2013
 Swapping

Computer system with 4 GB of main memory + a resident OS

taking 1 GB

The maximum size of user process is 3 GB.

However, many user processes are much smaller than 100

MB

Operating System Concepts – 9th Edition 8.35 Silberschatz, Galvin &Gagne ©2013
 Swapping
 To get an idea of the context-switch time:

Assume that the user process = 100 MB in size

Backing store is a hard disk with a transfer rate = 50 MB per

second.
The transfer of the 100 MB process to or from main memory =

100 MB / 50 MB per second = 2 seconds.

 Compared with 3 GB process, a 60 seconds is required for

swapping 3 GB.

3000 / 50 per second = 60 seconds.

Operating System Concepts – 9th Edition 8.36 Silberschatz, Galvin &Gagne ©2013
 Swapping (Cont.)
 Does the swapped-out process need to swap back into same physical
addresses?

 Depends on address binding method

 Plus consider pending I/O to or from process memory space.

 Can’t swap out as I/O would occur to wrong process.

 Standard swapping is not used in modern operating systems.

 It requires too much swapping time & provides too little execution
time to be
a reasonable memory-management solution.

 Modified versions of swapping are found on many systems (UNIX,

Linux, & Win)

 In one common variation, swapping is normally disabled.

 Start if the amount of free memory falls below a threshold amount.

 Disabled again when the amount

Operating 8.37of free memory increases.
System Concepts – 9th Edition Silberschatz, Galvin &Gagne ©2013
 Swapping (Cont.)
 Another variation involves swapping portions of processes —
rather than entire
processes — to decrease swap time.

 This modified forms of swapping work in conjunction with virtual

memory –
covered in chapter 9.

Operating System Concepts – 9th Edition 8.38 Silberschatz, Galvin &Gagne ©2013
 Context Switch Time including Swapping
 If next processes to be put on CPU is not in memory, need to
swap out a process & swap in target process – Context
switching.

 Context switch time can then be very high.

 100 MB process swapping to hard disk with transfer rate of 50

MB/sec:

1. Swap out time of 2000 ms  (2 seconds)

2. Swap in of same sized process  (2 seconds)

 Total context switch swapping time of 4000 ms (4 seconds) -

Very high

 Can reduce if reduce size of memory swapped – by knowing how

much memory really being used.

System calls to inform OS of memory use via

request_memory()
Operating System Concepts
th
– 9 Edition and8.39release_memory()
Silberschatz, Galvin &Gagne ©2013
 Swapping on Mobile Systems
 Swapping is not typically supported.
 Flash memory based.
 Small amount of space.
 Limited number of write cycles.
 Poor throughput between flash memory & CPU on mobile
platform.

 Instead of swapping use other methods to free memory if low.

 iOS asks apps to voluntarily relinquish allocated memory.

 Read-only data thrown out & reloaded from flash if
needed.
 Failure to free can result in termination of applications.

 Android terminates applications if low free memory, but first

writes application state to flash for fast restart.

 Both OSs support paging as discussed later.

Operating System Concepts – 9th Edition 8.40 Silberschatz, Galvin &Gagne ©2013
 Contiguous Allocation
 Main memory must support both OS & user processes.

 Because we have limited resource, must allocate memory

efficiently.

 Contiguous allocation is one early method.

 Main memory is usually divided into two partitions:

 Resident operating system

 Usually held in low memory with interrupt vector.
 Interrupt vector is used as memory location for
interrupt handler which prioritizes interrupts and
save them in queue.

 User processes
 Held in high memory.
 Each process contained in single contiguous section
of memory.
Operating System Concepts
th
– 9 Edition 8.41 Silberschatz, Galvin &Gagne ©2013
 Contiguous Allocation (Cont.)

 Relocation registers used to protect user processes from

each other.

 Relocation registers used to protect from changing

operating-system code & data.

 Base register contains value of smallest physical

address.

 Limit register contains range of logical addresses.

 Each logical address must be less than the limit
register.

 MMU maps logical address dynamically.

Operating System Concepts – 9th Edition 8.42 Silberschatz, Galvin &Gagne ©2013
 Hardware Support for Relocation & Limit Registers

Operating System Concepts – 9th Edition 8.43 Silberschatz, Galvin &Gagne ©2013
 Single Memory allocation
 Single Partition Allocation

 In this scheme OS is residing in low memory &

user processes are executing in higher memory.

 This single partition is available for user space

and only one job can be loaded in this user
space.

 The main memory consists of only one process

at a time because the user space is treated as a
single partition.
 It is simple.

 It is easy to understand and use.

 Disadvantages:
 It leads to poor utilization of processor &
memory.

 Users job is limited to the size of available

memory.
Operating System Concepts – 9th Edition 8.44 Silberschatz, Galvin &Gagne ©2013
 Multiple-partition allocation
 Multiple-partition Allocation
 One of the simplest methods for allocating memory is to
divide memory into several fixed sized partitions.

 There are two variations:

 Fixed equal-size partitions

 Fixed variable size partitions

Operating System Concepts – 9th Edition 8.45 Silberschatz, Galvin &Gagne ©2013
 Multiple-partition allocation
 Fixed Equal-size Partitions

 The OS divides the memory into fixed-size partitions.

 The OS occupies the low memory, and the rest of the

main memory is available for user space.

 The user space is divided into fixed partitions.

 The partition sizes are depending on the operating

system.

Operating System Concepts – 9th Edition 8.46 Silberschatz, Galvin &Gagne ©2013
 Multiple-partition allocation
 Fixed Variable size Partitions

 The OS treats the memory as a single chunk.

 The user space of the main memory is divided into several

partitions.

 Allocates parts of the memory as per the requirement of a

different process.

 The partition sizes are different lengths.

 The OS keeps a table indicating which partitions of

memory are available and which are occupied.

Operating System Concepts – 9th Edition 8.47 Silberschatz, Galvin &Gagne ©2013
 Multiple-partition allocation
 Multiple-partition allocation

 Degree of multiprogramming limited by number of partitions.

 Variable-partition sizes for efficiency (sized to a given process’ needs).
 Hole – holes of various size are scattered throughout memory.
 When a process arrives, it is allocated memory from a hole large enough
to accommodate it.
 Process exiting frees its partition, adjacent free partitions combined.
 OS maintains information about:
a) allocated partitions b) free partitions (hole)

Operating System Concepts – 9th Edition 8.48 Silberschatz, Galvin &Gagne ©2013
 Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?

 First-fit: Allocate the first hole that is big enough.

 Searching can start either at the beginning of the set of holes
or at the location where the previous first-fit search ended.
 From low memory and stop searching as soon as we find a
free partition that is large enough.

 Best-fit: Allocate the smallest hole that is big enough.

 Must search entire list.
 Produces the smallest leftover hole.
 Allocate the smallest partition that is big enough.

 Worst-fit: Allocate the largest hole.

 Must search entire list.
 Produces the largest leftover hole.
 More useful than the smaller leftover hole from a best-fit
First-fit approach.
& best-fit are better than worst-fit in terms of speed &
storage utilization.
Operating System Concepts – 9 Edition
th 8.49 Silberschatz, Galvin &Gagne ©2013
 Fragmentation
 Fragmentation occurs when most free blocks are too
small/large to satisfy any request perfectly.

 Fragmentation typically occurs because user processes

are constantly being loaded and unloaded from the main
memory.

 Fragmentation is a process of data storage in which

memory space is used inadequately, decreasing ability or
efficiency and sometimes both.

 Inability to use memory that is free

 This hole problem is known

Operating System 8.50
Concepts – 9th Edition as fragmentation.
Silberschatz, Galvin &Gagne ©2013
 Fragmentation
 External Fragmentation
 Total memory space exists to satisfy a request, but it is not
contiguous.
 Solution to the problem of external fragmentation is
compaction or paging.
 Shuffle the memory contents to place all memory together in
one large block.
 Compaction is time-consuming, and it is not always possible.

Operating System Concepts – 9th Edition 8.51 Silberschatz, Galvin &Gagne ©2013
 Fragmentation
 Internal Fragmentation

 Allocated memory may be slightly larger than requested

memory.

 This size difference is memory internal to a partition, but not

being used.

 First fit analysis reveals that given N blocks allocated, 0.5 N

blocks lost to fragmentation.

 1/3 may be unusable -> 50-percent rule

Operating System Concepts – 9th Edition 8.52 Silberschatz, Galvin &Gagne ©2013
 Fragmentation (Cont.)
 Reduce external fragmentation by compaction.

 Shuffle memory contents to place all free memory together in

one large block

 Compaction is possible only if relocation is dynamic & is done

at execution time.

 I/O problem
 Latch job in memory while it is involved in I/O

 Do I/O only into OS buffers.

 Now consider that backing store has same fragmentation

problems.

Operating System Concepts – 9th Edition 8.53 Silberschatz, Galvin &Gagne ©2013
 Segmentation
 Another way of dividing the addressable memory.
 Memory-management scheme that supports user view of
memory.
 It is a non-contiguous memory allocation technique.
 A segment can be defined as a logical grouping of
instructions.
 A program is a collection of segments.
 A segment is a logical unit such as:
 Main program
 Function
 Method
 Object
 Local variables, global variables
 Common block
 Stack
 Symbol table
 Arrays
Operating System 8.54 Silberschatz, Galvin &Gagne ©2013
 Concepts – 9 Edition
th
 User’s View of a Program

Process is broken into

segments of variable
size

Operating System Concepts – 9th Edition 8.55 Silberschatz, Galvin &Gagne ©2013
 Logical View of Segmentation

4
1
2

3
A segment can be
4 2
identified by:

•Segment number 3

•Segment offset

user space physical memory space

Operating System Concepts – 9th Edition 8.56 Silberschatz, Galvin &Gagne ©2013
 Logical View of Segmentation

Operating System Concepts – 9th Edition 8.57 Silberschatz, Galvin &Gagne ©2013
 Segmentation Architecture
 Logical address consists of a two tuple:
< segment-number, offset >,

 Segment table – maps two-dimensional physical addresses.

 Each table entry has:
 Base – contains the starting physical address where
the segments reside in memory.
 Limit – specifies the length of the segment.

 Segment-table base register (STBR) points to the segment

table’s location in memory.

 Segment-table length register (STLR) indicates number of

segments used by a program.
segment number s is legal if s < STLR
Operating System Concepts – 9th Edition 8.58 Silberschatz, Galvin &Gagne ©2013
 Segmentation Architecture (Cont.)
 Protection
 With each entry in segment table associate:
 Validation bit = 0  illegal segment, or 1 for legal
segment.
 Read/write/execute privileges.

 Protection bits associated with segments.

 Code sharing occurs at segment level.
 Since segments vary in length, memory allocation is a
dynamic storage-allocation problem (First-fit, Best-fit or
worst-fit).
 A segmentation example is shown in the following
diagram.

Operating System Concepts – 9th Edition 8.59 Silberschatz, Galvin &Gagne ©2013
 Segmentation Hardware

• Similar to the Hardware Support for Relocation & Limit

Registers.
• But with little modification for segmentation hardware.
• Convert logical to physical address
Operating System Concepts – 9th Edition 8.60 Silberschatz, Galvin &Gagne ©2013
 Segmentation

Operating System Concepts – 9th Edition 8.61 Silberschatz, Galvin &Gagne ©2013
 Paging
 Segmentation permits the physical address space of a
process to be
non-contiguous memory allocation.
 Paging is another memory management scheme that offers
this advantage.
 Paging avoids:
 External fragmentation
 Compaction

 Segmentation does not avoid the above.

 The backing store in swapping has the same fragmentation

problems.
 Paging is used in most OS.
 Paging is implemented through cooperation between the OS
& hardware.

 Paging works by writing data to, and reading

Operating System Concepts – 9th Edition 8.62 Silberschatz, Galvin &Gagne ©2013
 Paging
 Paging implementation involves breaking physical memory into
fixed-sized blocks frames.

 And breaking logical memory into blocks of the same size

pages.
 frame size always a power of 2 between 512 bytes &16 MB.

 When a process is to be executed its pages are loaded into

available memory frames from the backing store.

 The backing store is divided into fixed-sized blocks that are

the same size as the memory frames.

 Page size = Frame sizes

 The logical address space is totally separate from the physical

address space.

 Still have internal fragmentation.

Operating System Concepts – 9th Edition 8.63 Silberschatz, Galvin &Gagne ©2013
 Paging

Logical memory Physical memory

• Physical memory is RAM

• Logical memory encompasses the entire address space available to
a process, which may include both physical RAM and space on
secondary storage used as an extension of RAM when needed.
• The OS manages the mapping of logical addresses to physical
locations.
Operating System Concepts – 9 Edition
th 8.64 Silberschatz, Galvin &Gagne ©2013
 Paging
 A Process is divided into equal size of pages – Logical address
 Physical memory is divided in same equal size of frames – Physical
address
 Pages are scattered in frames.
 The frame sizes may vary depending on the OS.
 Non-contiguous memory allocation

No. of entries in the page table = no. of pages

in process.
Each entry of page table contains frame no. +
Operating System Concepts – 9th Edition 8.65 Silberschatz, Galvin &Gagne ©2013
 Paging

• The OS keeps track of all free

frames.

• To run a program of size N

pages, need to find N free
frames & load program.

• Set up a page table to translate

logical to physical addresses.

• Page table is maintained by the

OS.

• Page table is also stored in

memory
in a form of page.
Operating System Concepts – 9 Edition
th 8.66 Silberschatz, Galvin &Gagne ©2013
 Paging
• Page table is used to
map a process page to
a physical frame.

• Each page can be

stored in any frame.

• Page table size =

No. of entries in
Page table X 1 entry
size.
Or

• Page table size =

No. of pages in process
X 1 entry size.

Operating System Concepts – 9th Edition 8.67 Silberschatz, Galvin &Gagne ©2013
 Implementation of Page Table

Operating System Concepts – 9th Edition 8.68 Silberschatz, Galvin &Gagne ©2013
 Address Translation Scheme
 Address generated by CPU is divided into:
 Page number (p) – used as an index into a page table which
contains base address of each page in physical memory.

 Page offset (d) – combined with base address to define the

physical memory address that is sent to the memory unit.

page number page offset

Logical Address = Page number + page offset p d
m -n n
 If the address m = 10 bits and n = 4 bits, then
 p is 6 bits
 d is 4 bits.

 For given logical address space 2m page size 2n

 Logical address space = the collection of all logical addresses
= process size.

Operating System Concepts – 9th Edition 8.69 Silberschatz, Galvin &Gagne ©2013
 Address Translation Scheme
 Physical Address is divided into:
 Frame number ( f ): Number of bits required to represent
the frame of Physical Address Space or Frame number.

 Frame offset ( d ): Number of bits required to represent

particular word in a frame or frame size of Physical
Address Space or word number of a frame or frame offset.

 Physical Address = Frame number + offset

Operating System Concepts – 9th Edition 8.70 Silberschatz, Galvin &Gagne ©2013
 Paging Hardware
How to implement are paging?
•We use Page no. and offset
•Page no index into a page table.
•Page table hold the Frame number
•The offset index into the byte itself within the Page
•For physical address, we have Frame no and offset no.
•Frame no. index into correct Frame in physical memory

Operating System Concepts – 9th Edition 8.71 Silberschatz, Galvin &Gagne ©2013
 Paging Model of Logical & Physical Memory

Operating System Concepts – 9th Edition 8.72 Silberschatz, Galvin &Gagne ©2013
 Paging Example
Frame no.
4 bytes or
Page 0
line in each 0
page
Page 1 P2
1

Page 2 2

Page 3 3

CPU generates the address of G: 5 P0

P: 1 and d: 2

1.G is in Page 1 6 P1
2.Go to the table and find the frame no.
3.6 * page size 4 = 24.
4.Now go to address 24 in frame 6. 7
5.Inside page 1 it is offset d = 2 so it is the same d in
RAM
Operating System Concepts – 9th Edition 8.73 Silberschatz, Galvin &Gagne ©2013
 Paging Example
• If page size = 2 bytes

• What is the size of the process?

Answer: Process size = 2 * 4 (no. of pages in the
process) = 8 bytes.

• What is the physical memory size?

Answer: Physical memory size =
8 (frames) * 2 Bytes = 16 bytes.

• How many bits are required for logical addresses?

4 bytes = 22  2 bits

• How many bits are required for physical address?

8 bytes = 23  3 bits

Operating System Concepts – 9th Edition 8.74 Silberschatz, Galvin &Gagne ©2013
 Paging Example

• CPU generates Page no 11 and offset 0

• Translate to physical address 1110
(111+ 0) = 1110 for the first byte.
• And 1111 for the second byte
Operating System Concepts – 9th Edition 8.75 Silberschatz, Galvin &Gagne ©2013
 Paging Example
• CPU always generates logical address.
• Logical address :
• Page no.
• Byte no.
• How many bits are required for page numbering?
• This depends on how many pages we have
• If we have 4 pages, then we need 2 bits for page
numbering. 22
• If we have 16 pages then we need 4 bits for page
numbering. 24
• Logical address space = the collection of all logical
addresses = process size.

• Physical address space = the collection of all physical

Operating System Concepts – 9th Edition 8.76 Silberschatz, Galvin &Gagne ©2013
 Paging Example
• If we have 16 bytes logical address size, how many bits
are needed for addressing?
• Answer is 4 bits. (2^ 4 = 16).

• If we have 64-byte physical address size, how many bits

are needed for addressing?
• Answer is 6 bits. (2^ 6 = 64).

Operating System Concepts – 9th Edition 8.77 Silberschatz, Galvin &Gagne ©2013
 Paging Example
• CPU generate
logical address
101,
• find the physical
address
• Which page?
• Which byte?

• This address
belongs to page
10 & byte 1.
• Go to the page
table.
• Frame no. 011
• Check the byte
no. 1. in
physical
memory
• The result is f.
• So the physical
address is 011 +
1 = 0111
Operating System Concepts – 9th Edition 8.78 Silberschatz, Galvin &Gagne ©2013
 Paging (Cont.)
 Calculating internal fragmentation:
 Page size = 2,048 bytes
 Process size = 72,766 bytes
 35 pages (process size / Page size) + 1,086 bytes remaining so
we need 36 pages.
 Internal fragmentation = page size 2,048 - 1,086 = 962 bytes.
 Worst case fragmentation = 1 frame is 1 byte (page size + 1
byte) extra frame with 2047 bytes free space (internal
fragmentation)
 On average fragmentation = ½ frame size (½ 1 MB or ½ 2KB)

 So small frame sizes desirable? The problem is the page table

will be very big and will use more space in memory.
 Each page table entry takes memory to track.

 Page sizes growing over time from few MB to several GB)

 Solaris supports two-page sizes – 8 KB & 4 MB

 Process view & physical memory now very different.

 By implementation process can only access itsSilberschatz,

own memory. Galvin &Gagne ©2013
Operating System Concepts – 9th Edition 8.79
 Free Frames

Operating System Concepts – 9th Edition 8.80 Silberschatz, Galvin &Gagne ©2013
 Implementation of Page Table
 Page table is kept in main memory.

 How the CPU find the page table in memory?

 CPU uses 2 registers

 Page-table base register (PTBR) points to the page table.

 holds the starting physical address of page table.

 Page-table length register (PTLR) indicates size of the page

table.

 In this scheme every data/instruction access requires two

memory accesses.
1. One for the page table. To find the corresponding frame no.
2. One for the data / instruction. To access the memory word in
that frame.
 The two-memory access problem can be solved by the use of a
special fast-lookup hardware cache called
 Associative memory or Translation Look-aside Buffers (TLBs)

Operating System Concepts – 9th Edition 8.81 Silberschatz, Galvin &Gagne ©2013
 Implementation of Page Table
 Translation Lookaside Buffer (TLB).

 A specific cache used to maintain the record of recently

used virtual to physical memory transactions

 It is called a Translation Lookaside Buffer (TLB).

 It is comprised of page numbers and their corresponding

frame numbers that is stored in each TLB entry.

 Can be used to reduce the time taken to access the page

table.

 It is a memory cache which is closer to the CPU.

 The time taken by CPU to access TLB is less than the

time taken to access main memory.

Operating System Concepts – 9th Edition 8.82 Silberschatz, Galvin &Gagne ©2013
 Paging Hardware With TLB

Operating System Concepts – 9th Edition 8.83 Silberschatz, Galvin &Gagne ©2013
 Paging
 Advantages of Paging
 The memory management algorithm is easy to use.
 External Fragmentation is not required.
 Swapping between equal-sized pages and page frames
becomes easier.
 Disadvantages of Paging
 Internal fragmentation.
 Additional memory consumption by page tables.
 Memory reference overhead due to multi-level paging.

Operating System Concepts – 9th Edition 8.84 Silberschatz, Galvin &Gagne ©2013
 Two-Level Page-Table Scheme

Operating System Concepts – 9th Edition 8.85 Silberschatz, Galvin &Gagne ©2013
 Paging
 Process size = 4 B

 Page size = 2 Bytes

 What is the no. pages ?

Answer: 4 Bytes/ 2 Bytes = 2 Bytes

 Main memory size = 16 Bytes

 What is the frame size?

Answer: Frame size = 2 Bytes

 What is the no. of frames?

Answer: 16 Bytes / 2 Bytes = 8 bytes frames

Operating System Concepts – 9th Edition 8.86 Silberschatz, Galvin &Gagne ©2013
 Implementation of Page Table (Cont.)
 Some TLBs store address-space identifiers (ASIDs)
in each TLB entry – uniquely identifies each
process to provide address-space protection for
that process
 Otherwise need to flush at every context
switch
 TLBs typically small (64 to 1,024 entries)
 On a TLB miss, value is loaded into the TLB for
faster access next time
 Replacement policies must be considered
 Some entries can be wired down for permanent
fast access

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.87 Silberschatz, Galvin &Gagne ©2013
 Associative Memory

 Associative memory – parallel search

P a ge # F ra m e #

 Address translation (p, d)

 If p is in associative register, get frame # out
 Otherwise get frame # from page table in memory

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.88 Silberschatz, Galvin &Gagne ©2013
 Paging Hardware With TLB

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.89 Silberschatz, Galvin &Gagne ©2013
 Effective Access Time
 Associative Lookup =  time unit
 Can be < 10% of memory access time
 Hit ratio = 
 Hit ratio – percentage of times that a page number is
found in the associative registers; ratio related to
number of associative registers
 Consider  = 80%,  = 20ns for TLB search, 100ns for
memory access
 Effective Access Time (EAT)
EAT = (1 + )  + (2 + )(1 – )
=2+–
 Consider  = 80%,  = 20ns for TLB search, 100ns for
memory access
 EAT = 0.80 x 100 + 0.20 x 200 = 120ns
 Consider more realistic hit ratio ->  = 99%,  = 20ns for
TLB search, 100ns for memory access
(Out of Syllabus)
 EAT = 0.99 x 100 + 0.01 x 200 = 101ns

Operating System Concepts – 9th Edition 8.90 Silberschatz, Galvin &Gagne ©2013
 Memory Protection
 Memory protection implemented by associating
protection bit with each frame to indicate if read-
only or read-write access is allowed
 Can also add more bits to indicate page
execute-only, &so on
 Valid-invalid bit attached to each entry in the page
table:
 “valid” indicates that the associated page is in
the process’ logical address space, &is thus a
legal page
 “invalid” indicates that the page is not in the
process’ logical address space
 Or use page-table length register (PTLR)
 Any violations result in a trap to the kernel
(Out of Syllabus)

Operating System Concepts – 9th Edition 8.91 Silberschatz, Galvin &Gagne ©2013
 Valid (v) or Invalid (i) Bit In A Page Table

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.92 Silberschatz, Galvin &Gagne ©2013
 Shared Pages
 Shared code
 One copy of read-only (reentrant) code shared
among processes (i.e., text editors, compilers,
window systems)
 Similar to multiple threads sharing the same
process space
 Also useful for interprocess communication if
sharing of read-write pages is allowed
 Private code &data
 Each process keeps a separate copy of the
code &data
 The pages for the private code &data can
appear anywhere in the logical address space

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.93 Silberschatz, Galvin &Gagne ©2013
 Shared Pages Example

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.94 Silberschatz, Galvin &Gagne ©2013
 Structure of the Page Table
 Memory structures for paging can get huge using
straight-forward methods
 Consider a 32-bit logical address space as on
modern computers
 Page size of 4 KB (212)
 Page table would have 1 million entries (232 / 212)
 If each entry is 4 bytes -> 4 MB of physical address
space / memory for page table alone
 That amount of memory used to cost a lot
 Don’t want to allocate that contiguously in main
memory
 Hierarchical Paging
 Hashed Page Tables
 Inverted Page Tables
(Out of Syllabus)

Operating System Concepts – 9th Edition 8.95 Silberschatz, Galvin &Gagne ©2013
 Hierarchical Page Tables
 Break up the logical address space into
multiple page tables
 A simple technique is a two-level page
table
 We then page the page table

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.96 Silberschatz, Galvin &Gagne ©2013
 Two-Level Page-Table Scheme

Operating System Concepts – 9th Edition 8.97 Silberschatz, Galvin &Gagne ©2013
 Two-Level Paging Example
 A logical address (on 32-bit machine with 1K page size) is
divided into:
 a page number consisting of 22 bits
 a page offset consisting of 10 bits

 Since the page table is paged, the page number is further

divided into:
 a 12-bit page number
 a 10-bit page offset
 Thus, a logical address is as follows:

 where p1 is an index into the outer page table, &p2 is the

displacement within the page of the inner page table
 (Out of Syllabus)
Known as forward-mapped page table

Operating System Concepts – 9th Edition 8.98 Silberschatz, Galvin &Gagne ©2013
 Address-Translation Scheme

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.99 Silberschatz, Galvin &Gagne ©2013
 64-bit Logical Address Space

 Even two-level paging scheme not sufficient

 If page size is 4 KB (212)
 Then page table has 252 entries
 If two level scheme, inner page tables could be 2 10 4-byte
entries
 Address would look like

 Outer page table has 242 entries or 244 bytes

 One solution is to add a 2nd outer page table
 But in the following example the 2nd outer page table is
still 234 bytes in size
 &possibly 4 memory access to get to one physical
(Out of Syllabus)
memory location

Operating System Concepts – 9th Edition 8.100 Silberschatz, Galvin &Gagne ©2013
 Three-level Paging Scheme

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.101 Silberschatz, Galvin &Gagne ©2013
 Hashed Page Tables
 Common in address spaces > 32 bits
 The virtual page number is hashed into a page table
 This page table contains a chain of elements hashing to
the same location
 Each element contains (1) the virtual page number (2) the
value of the mapped page frame (3) a pointer to the next
element
 Virtual page numbers are compared in this chain searching
for a match
 If a match is found, the corresponding physical frame is
extracted
 Variation for 64-bit addresses is clustered page tables
 Similar to hashed but each entry refers to several pages
(such as 16) rather than 1
 Especially useful for sparse address spaces (where
memory references are non-contiguous &scattered)
(Out of Syllabus)
Operating System Concepts – 9th Edition 8.102 Silberschatz, Galvin &Gagne ©2013
 Hashed Page Table

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.103 Silberschatz, Galvin &Gagne ©2013
 Inverted Page Table
 Rather than each process having a page table
&keeping track of all possible logical pages, track all
physical pages
 One entry for each real page of memory
 Entry consists of the virtual address of the page
stored in that real memory location, with information
about the process that owns that page
 Decreases memory needed to store each page table,
but increases time needed to search the table when a
page reference occurs
 Use hash table to limit the search to one — or at most
a few — page-table entries
 TLB can accelerate access
 But how to implement shared memory?
 One mapping of a virtual address to the shared
(Out of Syllabus)
physical address

Operating System Concepts – 9th Edition 8.104 Silberschatz, Galvin &Gagne ©2013
 Inverted Page Table Architecture

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.105 Silberschatz, Galvin &Gagne ©2013
 Oracle SPARC Solaris
 Consider modern, 64-bit operating system example
with tightly integrated HW
 Goals are efficiency, low overhead
 Based on hashing, but more complex
 Two hash tables
 One kernel &one for all user processes
 Each maps memory addresses from virtual to
physical memory
 Each entry represents a contiguous area of mapped
virtual memory,
 More efficient than having a separate hash-table
entry for each page
 Each entry has base address & span (indicating the
number of pages the entry represents)
(Out of Syllabus)

Operating System Concepts – 9th Edition 8.106 Silberschatz, Galvin &Gagne ©2013
 Oracle SPARC Solaris (Cont.)
 TLB holds translation table entries (TTEs) for fast
hardware lookups
 A cache of TTEs reside in a translation storage
buffer (TSB)
 Includes an entry per recently accessed page
 Virtual address reference causes TLB search
 If miss, hardware walks the in-memory TSB looking
for the TTE corresponding to the address
 If match found, the CPU copies the TSB entry into
the TLB &translation completes
 If no match found, kernel interrupted to search
the hash table
– The kernel then creates a TTE from the
appropriate hash table &stores it in the TSB,
Interrupt handler returns control to the MMU,
(Out of Syllabus)
which completes the address translation.

Operating System Concepts – 9th Edition 8.107 Silberschatz, Galvin &Gagne ©2013
 Example: The Intel 32 &64-bit Architectures

 Dominant industry chips

 Pentium CPUs are 32-bit &called IA-32 architecture

 Current Intel CPUs are 64-bit &called IA-64 architecture

 Many variations in the chips, cover the main ideas here

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.108 Silberschatz, Galvin &Gagne ©2013
 Example: The Intel IA-32 Architecture
 Supports both segmentation &segmentation with
paging
 Each segment can be 4 GB
 Up to 16 K segments per process
 Divided into two partitions
 First partition of up to 8 K segments are
private to process (kept in local descriptor
table (LDT))
 Second partition of up to 8K segments shared
among all processes (kept in global descriptor
table (GDT))

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.109 Silberschatz, Galvin &Gagne ©2013
 Example: The Intel IA-32 Architecture (Cont.)

 CPU generates logical address

 Selector given to segmentation unit
 Which produces linear addresses

 Linear address given to paging unit

 Which generates physical address in main memory
 Paging units form equivalent of MMU
 Pages sizes can be 4 KB or 4 MB

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.110 Silberschatz, Galvin &Gagne ©2013
 Logical to Physical Address Translation in IA-32

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.111 Silberschatz, Galvin &Gagne ©2013
 Intel IA-32 Segmentation

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.112 Silberschatz, Galvin &Gagne ©2013
 Intel IA-32 Paging Architecture

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.113 Silberschatz, Galvin &Gagne ©2013
 Intel IA-32 Page Address Extensions
 32-bit address limits led Intel to create page address extension (PAE),
allowing 32-bit apps access to more than 4GB of memory space
 Paging went to a 3-level scheme
 Top two bits refer to a page directory pointer table
 Page-directory &page-table entries moved to 64-bits in size
 Net effect is increasing address space to 36 bits – 64GB of
physical memory

(Out of Syllabus)
Operating System Concepts – 9th Edition 8.114 Silberschatz, Galvin &Gagne ©2013
 Intel x86-64
 Current generation Intel x86 architecture
 64 bits is ginormous (> 16 exabytes)
 In practice only implement 48 bit addressing
 Page sizes of 4 KB, 2 MB, 1 GB
 Four levels of paging hierarchy
 Can also use PAE so virtual addresses are 48 bits
&physical addresses are 52 bits

(Out of Syllabus)

Operating System Concepts – 9th Edition 8.115 Silberschatz, Galvin &Gagne ©2013
 Example: ARM Architecture
 Dominant mobile platform
chip (Apple iOS &Google
Android devices for example)
 Modern, energy efficient, 32-
bit CPU
 4 KB &16 KB pages
 1 MB &16 MB pages (termed
sections)
 One-level paging for sections,
two-level for smaller pages
 Two levels of TLBs
 Outer level has two
micro TLBs (one data,
one instruction)
 Inner is single main TLB
 First inner is checked,
on miss outers are
checked, &on miss
page table walk
performed by CPU

(Out of Syllabus)
Operating System Concepts – 9th Edition 8.116 Silberschatz, Galvin &Gagne ©2013
 End of Chapter 8

Operating System Concepts – 9th Edition Silberschatz, Galvin &Gagne ©2013