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Unit I - 2

UEC1729-ASIC AND FPGA BASED DESIGN discusses semi-custom ASICs and programmable ASICs. It describes gate array based ASICs including channeled, channelless, and structured gate arrays which allow customization of interconnect layers. Programmable logic devices including PROM, PLA, PAL, CPLD and FPGA are also covered. CPLDs contain multiple PLDs and programmable interconnect on a single chip while FPGAs have configurable logic blocks and a flexible interconnect fabric. The document provides insights to help understand differences between semi-custom and programmable ASIC approaches.

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43 views28 pages

Unit I - 2

UEC1729-ASIC AND FPGA BASED DESIGN discusses semi-custom ASICs and programmable ASICs. It describes gate array based ASICs including channeled, channelless, and structured gate arrays which allow customization of interconnect layers. Programmable logic devices including PROM, PLA, PAL, CPLD and FPGA are also covered. CPLDs contain multiple PLDs and programmable interconnect on a single chip while FPGAs have configurable logic blocks and a flexible interconnect fabric. The document provides insights to help understand differences between semi-custom and programmable ASIC approaches.

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Janakiram V
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UEC1729-ASIC AND FPGA BASED DESIGN

Gate array based ASICs and Programmable ASICs

Presentation by
Dr. S. Aasha Nandhini, Assistant Professor, ECE
SSN College of Engineering
Session Meta Data

Author Dr. S. Aasha Nandhini

Reviewer

Version Number 1

Release Date 08 August 2023

2
Session Objectives

To Provide insights on semi custom ASICs and Programmable ASICs


Session Outcomes

At the end of the session you will be able to,

• Know about semi custom and programmable ASICs.


Outline

• Semi Custom ASIC- Gate array based ASIC

• Programmable logic devices

• FPGA
Gate Array Based ASIC
• In a gate array (sometimes abbreviated GA) or gate-array based ASIC the
transistors are predefined on the silicon wafer.
• The predefined pattern of transistors on a gate array is the base array.

• Only the top few layers of metal, which define the interconnect between
transistors, are defined by the designer using custom masks – masked
gate array.
• The designer chooses from a gate-array library of predesigned and pre-
characterized logic cells.
• The logic cells in a gate-array library are often called macros.
Channeled Gate Array
 Only the interconnect is customized.
 Similar to CBIC.
 One difference is that the space for
interconnect between rows of cells are fixed
in height in a channeled gate array-
adjusted in CBIC.
 The interconnect uses predefined spaces
between rows of base cells
 Manufacturing lead time is between two days
and two weeks
Channel less Gate Array
 Sea-of-Gates (SOG).
 Widely used – routing uses rows of unused
transistors.
 There are no predefined areas set aside for
routing - routing is over the top of the gate-
array devices
 Manufacturing lead time is between two days
and two weeks. Logic density -amount of
 When we use an area of transistors for routing logic that can be
implemented on a silicon
in a channel less array, we do not make any area is higher.
contacts to the devices lying underneath ,
we simply leave the transistors unused.
Structured Gate Array
 Embedded gate array.
 Only the interconnect is customized
 Custom blocks (the same for each design) can be
embedded
 These can be complete blocks such as a processor

or memory array, or
 An array of different base cells better suited to

implementing a specific function


 Manufacturing lead time is between two days and
two weeks.

• Advantage- Improved area efficiency and increased performance of a


CBIC with lower cost and faster turn around of an MGA.
• Disadvantage-embedded function is fixed.
Programmable ASICs
 Programmable Logic Devices
 No customized mask layers or logic cells
 PLDs use different technologies to allow programming of the
device.
 A single large block of programmable interconnect.
 A matrix of logic macrocells that usually consist of
programmable array logic followed by a flip-flop or latch
Programmable Logic Devices
• The simplest type of programmable IC is a read-only memory( ROM ). The
most common types of ROM use a metal fuse that can be blown
permanently (a programmable ROM or PROM ).
• An electrically programmable ROM , or EPROM , uses programmable MOS
transistors whose characteristics are altered by applying a high voltage.
• One can erase an EPROM either by using
another high voltage (an electrically erasable PROM , or EEPROM ) or by
exposing the device to ultraviolet light (UV-erasable PROM, or
UVPROM).
• There is another type of ROM that can be placed on any ASIC a mask-
programmable ROM (mask-programmed ROM or masked ROM).
• A masked ROM is a regular array of transistors permanently
programmed using custom mask patterns - embedded masked ROM is a
large, specialized, logic cell.
PROM
PLA

Sharing of AND terms across


multiple Ors

Programmable switches
between Horizontal and
Verticle Lines
PAL

Finite Combination of
AND/Ors

Fewer Switch Count

Faster than PLAs


Evolution of PLDs

• As technology has advanced, it has become possible to produce


devices with higher capacity.
• But, The structure of PALs grow too quickly in size as number of
inputs is increased and thus its not possible to produce PAL devices
with large capacity.
• So integration of multiple PLDs onto a single chip which is
called CPLD.
CPLD ( Complex PLD)

• CPLDs can be thought of as multiple PLDs (plus some


programmable interconnect) in a single chip.
• The larger size of a CPLD allows you to implement either more
logic equations or a more complicated design.
• Because CPLDs can hold larger designs than PLDs, their potential
uses are more varied.
CPLD

Logic blocks are themselves comprised of macrocells and interconnect


wiring, just like an ordinary PLD.

Unlike the programmable interconnect within a PLD, the switch matrix


within a CPLD may or may not be fully connected
CPLD

• Traditionally, CPLDs have been chosen over FPGAs whenever


high-performance logic is required, Because of its less flexible
internal architecture, the delay is more predictable and usually
shorter.
FPGA

• FPGAs are the newest member of the ASIC family and are rapidly
growing in , replacing TTL in microelectronic systems.
• Even though an FPGA is a type of gate array, we do not consider the term
gate-array based ASICs to include FPGAs.
• An FPGA is usually just larger and more complex than a PLD.
• In fact, some vendors that manufacture programmable ASICs call their
products as FPGAs and some call them as complex PLDs .
Field-programmable gate array (FPGA) die
CLB

• In general, a logic block (CLB) consists of a few logical cells.

• A typical cell consists of a 4-input Lookup table (LUT), a Full adder (FA)
and a D-type flip-flop

• In normal mode those are combined into a 4-input LUT through the
left mux.
• In arithmetic mode, their(LUT) outputs are fed to the FA. The selection of
mode are programmed into the middle mux.
Interconnects

• Each wiring segment spans only one logic block before it


terminates in a switch box.
• By turning on some of the programmable switches within a switch
box, longer paths can be constructed.
• For higher speed interconnect, some FPGA architectures use
longer routing lines that span multiple logic blocks.
Interconnects

• More detailed View


Detailed ViewInterconnects

• More detailed View


Field Programmable Gate Array

ASIC gives high performance at cost of inflexibility.

Processor is very flexible but not tuned to the


application.

Reconfigurable hardware is a nice compromise


Test Your Understanding
1. Can you compared CPLDs and FPGAs in terms of
•Architecture
•Density
•Speed
•Interconnect
•Power consumption
References
Text book:
1.Michael John Sebastian Smith, Applications Specific Integrated Circuits,
Pearson Education, Ninth Indian Reprint, Thirteenth Edition, 2004.

E-references:
1.https://www.microchip.com/en-us/products/fpgas-and-plds
2.https://link.springer.com/book/10.1007/978-1-349-14003-9
3.https://resources.pcb.cadence.com/blog/2019-cpld-vs-fpga-which-do-you-
need-for-your-digital-system
Thank you !

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