Multiprocessors—Synchronization

Synchronization

• How to synchronize processes?

– Need to protect access to shared data to avoid problems
like race conditions
– Typical example: Updating a shared account balance.
Problem below?

Processor 1 Processor 2
lw $t0,balance lw $t2,balance
lw $t1,amount lw $t3,amount
add $t0,$t0,t1 sub $t2,$t2,t3
sw $t0,balance sw $t2,balance
 Synchronization

• Why Synchronize? Need to know when it is safe for

different processes to use shared data
• Issues for Synchronization:
– Uninterruptable instruction to fetch and update memory (atomic
operation);
– User level synchronization operation using this primitive;
– For large scale MPs, synchronization can be a bottleneck;
techniques to reduce contention and latency of synchronization
 Hardware Synchronization

• For large scale MPs, synchronization can be a

bottleneck
– Contention adds additional delays, latency is potentially
great
• Hardware primitives needed
– all solutions based on "atomically inspect and update a
memory location"
• Higher level synchronization solutions can be
build on top of the basic hardware primitives
– Locks, barriers
– Generally employed by the system software not the
programmer directly
 Uninterruptable Instruction to
Fetch and Update Memory
• Atomic exchange: interchange a value in a register for a
value in memory
0 => synchronization variable is free
1 => synchronization variable is locked and unavailable
– Set register to 1 & swap
– New value in register determines success in getting lock 0 if
you succeeded in setting the lock (you were first)
1 if other processor had already claimed access
– Key is that exchange operation is indivisible
• Test-and-set: tests a value and sets it if the value passes the
test
• Fetch-and-increment: it returns the value of a memory
location and atomically increments it
– 0 => synchronization variable is free
 Uninterruptable Instruction to
Fetch and Update Memory
• Hard to have read & write in 1 instruction: use 2 instead
• Load linked (or load locked) + store conditional
– Load linked returns the initial value
– Store conditional returns 1 if it succeeds (no other store to same memory location since
preceeding load) and 0 otherwise
• Example doing atomic swap with LL & SC:
try: mov R3,R4 ; mov exchange value
ll R2,0(R1) ; load linked
sc R3,0(R1) ; store
beqz R3,try ; branch store fails
mov R4,R2 ; put load value in R4
• Example doing fetch & increment with LL & SC:
try: ll R2,0(R1) ; load linked
addi R2,R2,#1 ; increment (OK if reg–reg)
sc R2,0(R1) ; store
beqz R2,try ; branch store fails
 User Level Synchronization—Operation
Using Swap Primitive
• Spin locks: processor continuously tries to acquire, spinning around a
loop trying to get the lock
li R2,#1
lockit: exch R2,0(R1) ;atomic exchange
bnez R2,lockit ;already locked?
• What about MP with cache coherency?
– Want to spin on cache copy to avoid full memory latency
– Likely to get cache hits for such variables
• Problem: exchange includes a write, which invalidates all other copies;
this generates considerable bus traffic
• Solution: start by simply repeatedly reading the variable; when it changes,
then try exchange (“test and test&set”):
try: li R2,#1
lockit: lw R3,0(R1) ;load var
bnez R3,lockit ;not free=>spin
exch R2,0(R1) ;atomic exchange
bnez R2,try ;already locked?
 Steps for Invalidate Protocol
Step P0 $ P1 $ P2 $ Bus/Direct
activity
1. Has lock Sh spins Sh spins Sh None
2. Lock<– 0 Ex Inv Inv P0 Invalidates
lock
3. Sh miss Sh miss Sh WB P0; P2 gets
bus
4. Sh waits Sh lock = 0 Sh P2 cache filled
5. Sh lock=0 Sh exch Sh P2 cache
miss(WI)
6. Inv exch Inv return=0 Ex P2 cache filled;
Inv
lock = 1
7. Inv return=1 Ex locked Inv P1 cache
miss;WB P2
lock = 1
 Simpler Lock Implementation

lockit: ll R2,0(R1) ;load linked

bnez R2,lockit ;not free=>spin
li R2,#1 ;locked value
sc R2,0(R1) ;store
beqz R2,lockit ;branch if store fails