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Unit 3 - DECA Complete

The document discusses basic computer organization including CPU, memory, and I/O subsystems and their interconnection via buses. It describes the components of the CPU including the register section, ALU, and control unit. It also covers topics like instruction codes, addressing modes, effective addresses, and computer registers.

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0% found this document useful (0 votes)
94 views69 pages

Unit 3 - DECA Complete

The document discusses basic computer organization including CPU, memory, and I/O subsystems and their interconnection via buses. It describes the components of the CPU including the register section, ALU, and control unit. It also covers topics like instruction codes, addressing modes, effective addresses, and computer registers.

Uploaded by

manjilasingha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
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Digital Electronics and Computer Architecture (DECA)

Digital Electronics (Unit-3):


(Complete Unit)
Computer Organization: Introduction to Computer Organization &
Architecture, Basic Computer Organization, Instruction Codes, Computer Registers, Computer
Instructions, Memory, Reference, Register Reference and I/O Instructions, instruction Set
Completeness, Timing and Control, Instruction Cycle, Process to determine the type of
instructions, Input-Output and Program Interrupts.

B.E.-CSE 1st Sem.

Department of Interdisciplinary Courses in Engineering (DICE)


&
Department of Computer Science and Engineering
1
INTRODUCTION TO COMPUTER
ORGANIZATION
1. BASIC COMPUTER ORGANIZATION:
The basic computer organization has three main components:
 CPU
 Memory subsystem
 I/O subsystem.

The generic organization of these components is shown in the figure below.

Fig 1.1 Generic computer Organization


System bus:
Physically the bus is a set of wires. The components of a computer are connected to the buses. To send
information from one component to another the source component outputs data on to the bus. The
destination component then inputs the data from bus.
The system has three buses
 Address bus
 Data bus
 Control bus
 The uppermost bus in this figure is the address bus. When the CPU reads data or instructions from or
writes data to memory, it must specify the address of the memory location it wishes to access.

 Data is transferred via the data bus. When CPU fetches data from memory it first outputs the memory
address on to its address bus. Then memory outputs the data onto the data bus. Memory then reads
and stores the data at the proper locations.

 Control bus carries the control signal. Control signal is the collection of individual control signals.
These signals indicate whether data is to be read into or written out of the CPU.
CPU ORGANIZATION:

Central processing unit (CPU) is the electronic circuitry within a computer that carries out the instructions of a
computer program by performing the basic arithmetic, logical, control and input/output (I/O) operations specified by the
instructions.

In the computer all the major components are connected with the help of the system bus.

Data bus : Data bus is used to shuffle data between the various components in a computer system.

Address bus : To differentiate memory locations and I/O devices the system designer assigns a unique memory address to
each memory element and I/O device. When the software wants to access some particular memory location or I/O device
it places the corresponding address on the address bus. Circuitry associated with the memory or I/O device recognizes
this address and instructs the memory or I/O device to read the data from or place data on the data bus. Only the device
whose address matches the value on the address bus responds.
Control bus : The control bus is an eclectic collection of signals that control how the processor communicates with the
rest of the system. The read and write control lines control the direction of data on the data bus
When both contain logic one the CPU and memory-I/O are not communicating with one another.
If the read line is low (logic zero) the CPU is reading data from memory (that is the system is transferring data from
memory to the CPU).
If the write line is low the system transfers data from the CPU to memory.
The CPU controls the computer. It fetches instructions from memory, supply the address and control signals needed by
the memory to access its data.

Internally, CPU has three sections as shown in the fig below

Fig 1.2: CPU Organization


 The register section, as its name implies, includes a set of registers and a bus or other communication mechanism.
 The register in a processor’s instruction set architecture are found in the section of the CPU.
 The system address and data buses interact with this section of CPU. The register section also contains other
registers that are not directly accessible by the programmer.
 The fetch portion of the instruction cycle, the processor first outputs the address of the instruction onto the address bus.
The processor has a register called the “program counter”.
 The CPU keeps the address of the next instruction to be fetched in this register. Before the CPU outputs the address on to
the system bus, it retrieves the address from the program counter register.
 At the end of the instruction fetch, the CPU reads the instruction code from the system data bus.
 It stores this value in an internal register, usually called the “instruction register”.
 The arithmetic / logic unit (or) ALU performs most arithmetic and logic operations such as adding and ANDing values. It
receives its operands form the register section of the CPU and stores its result back in the register section.
 Just as CPU controls the computer, the control unit controls the CPU. The control unit receives some data values
from the register unit, which it used to generate the control signals. This code generates the instruction codes &
the values of some flag registers.
 The control unit also generates the signals for the system control bus such as READ, WRITE, I/O signals.
Instruction Codes

9
Instruction Codes
● The organization of the computer is defined by its internal registers, the timing and
control structure, and the set of instructions that it uses.

● A computer instruction is a binary code that specifies a sequence of micro-operations


for the computer.

● An instruction code is a group of bits that instruct the computer to perform a specific
operation.

● Instruction code is usually divided into two parts.


○ Operation part - Group of bits that define such operations as add, subtract,
multiply, shift, and complement.
○ Address part - Contains registers or memory words where the address of operand
is found or the result is to be stored.

● Each computer has its own instruction code format.

10
Operation Code
▪ The operation code (op-code) of an instruction is a group of bits that define
such operations as add, subtract, multiply, shift, and complement.

▪ The number of bits required for the operation code of an instruction depends
on the total number of operations available in the computer (n bits for 2n
operations).

11
Stored Program Organization

o Simplest way to organize computer is to have one processor


register(Accumulator AC) and an instruction code format with two parts:

○ First-Operation to be performed
○ Second – Address

o The memory address tells the control where to find an operand in memory.

o This operand is read from memory and used as the data to be operated on
together with the data stored in the processor register.

12
Stored Program Organization

● Instructions are stored in one section of


the memory and data in another.

● For a memory unit with 4096 words we


need 12 bits to specify an address since
212=4096.

● 4 bits are available for opcode to specify


one out of 16 possible operations.

13
Steps

▪ The control reads a 16-bit instruction from the program portion of memory.

▪ It uses the 12-bit address part of the instruction to read a 16-bit operand from
the data portion of memory.

▪ It then executes the operation specified by the operation code.

▪ The operation is performed with the memory operand and the content of AC.

14
Direct and Indirect Addressing Modes

❑ Following Addressing Modes are used


for address portion of the instruction code.

○ Immediate- The address part


specifies an operand.
Eg: ADD 5
○ Direct- The address part specifies the
address of an operand.
○ Indirect- The address part specifies
a pointer(another address) where the
address of the operand can be found.

❑ One bit of the instruction code(I) can be


used to distinguish between a direct and
an indirect address.
15
Effective Address

It is the address of the operand in a


computation-type instruction or the target
address in a branch-type instruction.

The effective address in the instruction of the


figures are 457 and 1350.

16
Computer Registers

17
Basic Computer
Registers and
Memory

18
Computer Registers
Need of Registers?
▪ Computer instructions are normally stored in consecutive memory locations
and are executed sequentially one at a time.
▪ The control reads an instruction from a specific address in memory and
executes it. It then continues by reading the next instruction in sequence and
executes it, and so on.
▪ This type of instruction sequencing needs a counter to calculate the address
of the next instruction after execution of the current instruction is completed.
▪ It is also necessary to provide a register in the control unit for storing the
instruction code after it is read from memory.
▪ The computer needs processor registers for manipulating data and a register
for holding a memory address.

19
List of Registers for Basic Computer

20
Computer Instructions

21
Instruction Format
▪ The basic computer has three instruction code formats each having 16 bits:

○ Memory reference instructions


○ Register reference instructions
○ I/O instructions

▪ The opcode part of the instruction contains three bits and the meaning of the
remaining 13 bits depends on the operation code encountered.

22
Memory Reference Instructions

▪ Bits 0-11 for specifying address.

▪ Bits 12-14 for Opcode.

▪ 15th bit specifies addressing modes. (0 for direct and 1 for indirect)

23
Register Reference Instructions
▪ Recognized by the operation code 111 with a 0 in the 15th bit of the
instruction.
▪ Specifies an operation on or a test of the AC register.
▪ An operand from memory is not needed.
▪ Therefore the 12 bits are used to specify the operation to be executed.

Eg:
○ CLA - 7800 : Clear AC
○ CLE - 7400 : Clear E

24
Input-Output Instructions
▪ These instructions are needed for transferring information to and from AC
register.
▪ Recognized by the opcode 111 and a 1 in the 15th bit.
▪ Bits 0-11 specify the type of I/O Operation performed.

Eg:
○ INP - F800 : Input characters to AC
○ OUT - F400 : Output characters from AC

25
Basic Computer Instructions

26
Instruction Set Completeness

▪ The set of instructions are said to be complete if the computer includes a


sufficient number of instructions in each of the following categories:

• Arithmetic, logical, and shift instructions.

• Instructions for moving information to and from memory and processor


registers.

• Program control instructions.

• Input and output instructions.

27
Timing and Control
• The timing for all register in computer is controlled by a master
clock generator.
• Control signals are generated in the control unit and provide
control inputs for the multiplexers, common bus, processor
registers, and accumulator.
• Two major types of control organizations:
-Hardwired Control
- Microprogrammed Control
• Hardwired control is implemented with gates, flip-flops,
decoders, and other digital circuits.
• In microprogrammed control, control information is stored in
control memory, and any required change or modification can
be done by updating the microprogram in the control memory.
28
Hardwired Control unit of basic Computer
.

29
Example of Control Timing Signals
. At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC0

30
Instruction Cycle
• A program residing in the memory unit of computer consists of
a sequence of instructions.
• The program is executed in the computer by going through a
cycle for each instruction.
• Each instruction cycle is subdivided into sequence of subcycles
of phases.
– 1. Fetch an instruction from memory
– 2. Decode the instruction
– 3. Read the effective address from memory if the information has an
indirect address.
– 4. Execute the instruction
• Upon completion of step 4, control goes back to step 1 to fetch, decode and
execute the next instruction.
• This process continues indefinitely unless a HALT instruction is encountered.
31
Fetch and Decode
• Initially program counter PC is loaded with the address of first
instruction in the program. And sequence counter (SC) is
cleared to 0.
• After each clock pulse, SC is incremented by 1.
• The micro operations for the fetch and decode phase can be
specified by following register transfer statement.

32
Cont…
.

• Place the content


of PC onto the bus
by making the bus
selection inputs
S2 S1 S0=010.

• Transfer the
content of the bus
to AR.

33
Determine the Type of Instruction
• During time T3, the control unit determines the type of instruction that was just read from the
memory.

• Purpose is to determine the type of instruction by control unit whether it is


i. Memory Reference Instruction
ii. Register Reference Instruction
iii. I/O Instruction

34
Determine the Type of
Instruction- Flow Chart

35
Memory reference instruction
Memory reference instruction

• Memory reference instructions are those commands or instructions


which are in the custom to generate a reference to the memory and
approval to a program to have an approach to the commanded
information and that states as to from where the data is cache
continually. These instructions are known as Memory Reference
Instructions.
• There are seven memory reference instructions which are as follows &
AND
• The AND instruction implements the AND logic operation on the bit
collection from the register and the memory word that is determined by
the effective address. The result of this operation is moved back to the
register.
ADD
• The ADD instruction adds the content of the memory word that is
denoted by the effective address to the value of the register.
LDA

The LDA instruction shares the memory word denoted by the effective address to the
register.

STA
STA saves the content of the register into the memory word that is defined by the
effective address. The output is next used to the common bus and the data input is
linked to the bus. It needed only one micro-operation.
Memory reference
instruction
BUN
The Branch Unconditionally (BUN) instruction can send the instruction that is
determined by the effective address. They understand that the address of the next
instruction to be performed is held by the PC and it should be incremented by one
to receive the address of the next instruction in the sequence. If the control needs
to implement multiple instructions that are not next in the sequence, it can
execute the BUN instruction.
BSA
BSA stands for Branch and Save return Address. These instructions can branch a part
of the program (known as subroutine or procedure). When this instruction is
performed, BSA will store the address of the next instruction from the PC into a
memory location that is determined by the effective address.
ISZ
The Increment if Zero (ISZ) instruction increments the word determined by effective
address. If the incremented cost is zero, thus PC is incremented by 1. A negative
value is saved in the memory word through the programmer. It can influence the
zero value after getting incremented repeatedly. Thus, the PC is incremented and
the next instruction is skipped.
1. AND to AC

⚫ This is an instruction that performs the AND logic


operation on pair of bits in AC and the Memory word
specified by effective address.
⚫ The result of the operation is transferred to AC.
⚫ The microoperation performed this operation are:

⚫ Total time cycle = 6


2. ADD to AC

⚫ This instruction adds the content of memory word


specified by effective address to the value to AC.
⚫ The sum is transferred to AC and the output carry Cout
is transferred to the E (extended AC) flip-flop.
⚫ The microoperation performed this operation are:

⚫ Total time cycle = 6


3. LDA : Load to Ac

⚫ This instruction transferred the content of memory


word specified by effective address to the AC.

⚫ The microoperation performed this operation are:

⚫ Total time cycle = 6


4. STA : Store AC

⚫ This instruction store the content of AC in to the


memory word specified by effective address .
⚫ The microoperation performed this operation are:

⚫ Total time cycle = 5


5. BUN: Branch Unconditionally

⚫ This instruction transfers the program to the


instruction specified by the effective address. PC holds
the address of instruction to be read from memory in
the next instruction cycle.
⚫ It allows the programmer to specify an instruction out
of sequence.
⚫ The microoperation performed this operation are:

⚫ Total time cycle = 5


6. BSA: Branch and Save return Address

⚫ This instruction is useful for branching to a portion of


the program called a subroutine or procedure.
⚫ 1st it stores the address of next instruction in sequence
into memory location specified by effective address.
Then effective address plus one is transferred to PC to
serve the address of next instruction.
⚫ The microoperation performed this operation are:

⚫ Total time cycle = 6


Input-Output and Interrupt
Introduction

 A Computer can serve no useful purpose unless it


communicates with the external environment.
 Instructions and data stored in memory must come from some
input device.
 Computational results must be transmitted to user through
some output device.
 Commercial computers include many types of input and
output devices.
 To demonstrate the most basic requirements for input and
output communication, we will use as a illustration a terminal
unit with a keyboard and printer.
Input-Output Configuration

 The terminal sends and receives serial information.


 Each quantity of information has eight bits of an alphanumeric code.
 The serial information from the keyboard is shifted into the input
register INPR.
 The serial information for printer is stored in output register OUTR.
 These two registers communicate with communication interface
serially and with the AC in parallel.
Input-Output Configuration
Input-Output Flags

• 1 bit input flag FGI is a control flip-flop. The flag bit is 1 when new information
is available in input device and cleared to zero when accepted by computer.
• Flag is used to synchronize the timing rate difference between input device
and computer.
• Initially FGI is set to 0. when a key is struck in the keyboard, an 8-bit
alphanumeric code is shifted in to INPR and the input flag FGI is set to 1.

• The output register OUTR works similarly but the direction of information flow
is reversed.
• Initially, the output flag FGO is set to 1.
• Computer checks FGO, and if it is 1, the information from AC is transferred in
a parallel to OUTR and FGO is cleared to 0.
Input-Output
Instructions.
 For this type of information I=1, and
D7 (i.e. IR(12-14)=111)
 For basic Computer only 6 input-output instruction.
Program Interrupt
 An alternative to the programmed controlled procedure is to let the
external device inform the computer when it is ready for the transfer.
 In the meantime computer can be busy with other tasks.
 This type of transfer use the interrupt facility. While computer is
running the program, it does not check the flags, however when a flag is
set then computer receives an interrupt.
 The interrupt enable flip-flop IEN can be set and cleared with two
instructions.
 When IEN is cleared to zero (with IOF instruction), the flag can not
interrupt the computer.
 When IEN is cleared to 1 (with ION instruction), the computer can be
interrupted.
Flowchart of Interrupt cycle
Interrupt cycle

 Here the modified fetch and decode phase of


interrupt cycles as follow:
Question Practice

1. A computer uses a memory unit with 65536 words of 32 bits each. A binary
instruction code is stored in one word of memory. The instruction has four
parts: an indirect bit, an operation code, a register code part to specify one
of 1024 registers and an address part.
(i). How many bits are there in the operation code, the register part, indirect bit
and the address part?
(ii). Draw an instruction word format and indicate the number of bits in each
part. •Memory unit with word size 65536, So number of address bits = 16
Resister 1024, Register code 10 bits.
Indirect bit 1 bit.
So, operation code = (32-10-16-1)=5 bits

Total 32 bits.
1 5 10 16
I Opcode Register Address

55
2. An instruction at address 021 in the basic computer has an address part
equal to 083 (all numbers are in hexadecimal). The memory word at
address 083 contains the operand C73A and the content of AC
(Accumulator) is B239. Determine the contents of the registers at the end
of the execute phase: PC (Program Counter), AR (Address Register), AC and
IR (Instruction Register). Implement the problem using following operation
codes (Hexadecimal code):
i) AND (0083)
ii) CMA (7200)
iii) INC (7800)
iv) BUN (4520)

56
Ans. 2
Step 1

PC AR DR AC IR
Initial 021 083 C73A B239 0083
AND
CMA
INC
BUN

57
Ans. 2

PC AR DR AC IR
Initial 021 083 C73A B239 0083
AND 022 083 --- 8238 0083
CMA 022 083 ---- 4DC6 7200
INC 022 083 ---- B23A 7800
BUN 083 083 B239 4520

58
MCQs

1) Who developed the basic architecture of computer?

a) Blaise Pascal
b) Charles Babbage
c) John Von Neumann
d) None of the above

2) Which of the following allows simultaneous write and read operations?


a) ROM
b) EROM
c) RAM
d) None of the above

59
3) Which of the following is not considered as a peripheral device?
a)CPU
b)Keyboard
c)Monitor
d)All of the above
4) Computer address bus is -
a)Multidirectional
b)Bidirectional
c)Unidirectional
d)None of the above

60
5) Which of the following is a way in which the components of a computer are connected to each
other?
a)Computer parts
b)Computer architecture
c)Computer hardware
d)None of the above

6) Which of the following computer bus connects the CPU to a memory on the system board?
a) Expansion bus
b) Width bus
c) System bus
d)None of the above

61
7) Which of the following memory unit communicates directly with the CPU?
a) Auxiliary memory
b) Main memory
c) Secondary memory
d) None of the above

8) In which of the following form the computer stores its data in memory?
a) Hexadecimal form
b) Octal form
c) Binary form
d) Decimal form

62
Answer Key

1. C
2. C
3. A
4. C
5. B
6. C
7. B
8. C
63
Question Practice

1. MRI Indicates
a) Memory Reference Information
b) Memory Reference Instruction
c) Memory Registers Instruction
d) Memory Registers Information

2. In which of the following form the computer stores its data in


memory?
e) Hexadecimal form
f) Octal form
g) Binary form
h) Decimal form
64
Cont…
.
Q. 3 A computer uses the memory with unit of 256K words of 32 bit each. A binary
instruction of code stored one word of the memory. The Instruction has four parts
which are Indirect bit, register code, an operation code and address part with 64
registers. How many bit are there in operation code?

65
Cont..
Q. 4 The content of AC is A937, the content of PC in basic computer is 021, what will the value of AC and PC after
performing
. CIR ?

Answer: D49B

66
Cont..

67
Cont..

68
Thank You

69

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