Design Technologies for Integrated Systems

Giovanni De Micheli
Integrated Systems Centre
EPF Lausanne

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© Giovanni De Micheli – All rights reserved
 Electronic systems

 Systems on chip are everywhere

 Technology advances enable increasingly more complex designs

 Challenges:
 Ride the technology wave
 Cope with design complexity

(c) Giovanni De Micheli 2

 Application of microcontrollers
250
226

Average number of microcontroller ICs

Home
200

150

100

69 Office 42
50
18
35
2 Auto
14
0
1970 1980 1990 2000

Home Office Automobile

Appliances Camcorder Telephones Drive by wire
Intercom Remote controls Computers Trip computer
Telephones Video games Security system Air bags
Security system Cellular phones Fax machines ABS
Garage door opener Musical instruments Copier Instrumentation
Answering machines Sewing machines Printers Security system
Fax machines Lighting control Remote control Transmission control
Home computers Paging Pagers Entertainment
TVs Cameras Climate control
Cable TV tuner Exercise equipment Keyless entry
VCR Microwave oven Cellular phone
GPS

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 Moore’s law in avionics

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 Integrated circuits

 Systems on Chip (SoC)

 Multi-processing SoCs (MPSoCs)
 Systems in a package (SiP)

 Silicon technology (CMOS)

 Down scaling of feature sizes
 Nanotechnologies on the horizon …
 Different design styles
 To address performance and cost issues

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 Integrated Circuit Design Styles

Digital Circuit Implementation Approaches

Custom Semicustom

Cell-based Array-based

Standard Cells Pre-diffused Pre-wired

Macro Cells
Compiled Cells (Gate Arrays) (FPGA's)

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 The Custom Approach

Intel 4004

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Courtesy Intel
 Transition to Automation and Regular Structures

Intel 4004 (‘71)

Intel 8080 Intel 8085

Intel 8286 Intel 8486

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Courtesy Intel
 Standard Cell - Example

3-input NAND cell

(from ST Microelectronics):
C = Load capacitance
T = input rise/fall time

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 Cell-based Design (or standard cells)

Routing channel
requirements are
reduced by presence
of more interconnect
layers

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 Standard Cell – The New Generation

Cell-structure
hidden under
interconnect layers

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 “Soft” MacroModules

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Synopsys DesignCompiler
 Gate Array — Sea-of-gates

Uncommited
Cell

Committed
Cell
(4-input NOR)

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 Field-Programmable Gate Arrays
Fuse-based

Standard-cell like
floorplan

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 Field Programmable Gate Arrays
Xilinx 4000 Interconnect Architecture

12 Quad

8 Single

4 Double

3 Long

Direct
CLB 2 Connect

3 Long
12 4 4 8 4 8 4 2

Quad Long Global Long Double Single Global Carry Direct

Clock Clock Chain Connect

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Courtesy Xilinx
 Heterogeneous Programmable Platforms
FPGA Fabric

Embedded memories
Embedded PowerPc

Hardwired multipliers

Xilinx Vertex-II Pro

High-speed I/O
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Courtesy Xilinx
 Computer-aided design

 Enabling design methodology

 Support large scale system design
 Design optimization, centering and trade-off
 Reduce design time and time to market

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 Microelectronic circuit design

 Conceptualization and modeling

 Hardware description languages
 Synthesis and optimization
 Model refinement
 Validation
 Check for correctness

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 Synthesis history

 Few logic synthesis algorithms and tools existed in the 70’s

 Link to place and route for automatic design

 Innovative methods at IBM, Bell Labs, Berkeley, Stanford
 First prototype synthesis tools in the early 80s
 YLE [Brayton], MIS [Berkeley], Espresso
 First logic synthesis companies in the late 80’s
 Synopsys and others

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 Modeling abstractions

 Architectural level
 Operations implemented
by resources
 Logic level
 Logic functions implemented
by gates
 Geometrical level
 Transistors and wires

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 Circuit synthesis

 Architectural-level synthesis
 Determine macroscopic structure
 Interconnection of major building blocks

 Logic-level synthesis
 Determine the microscopic structure
 Interconnection of logic gates

 Physical design
 Geometrical-level synthesis
 Determine positions and connections

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 Synthesis levels

b-view s-view

a-synthesis
a-
level

l-synthesis
l-level

p-design
g-level

p-view

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 Synthesis and optimization
 Synthesis with no optimization has no value

 Optimization is the means to outperform manual design

 Objectives
 Performance
 Frequency, latency, throughput
 Energy consumption
 Area (yield and packaging cost)
 Testability, dependability, …
 Optimization has multiple objectives
 Trade off
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 Combinational circuit optimization

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 Optimization trade-off in sequential circuits
Area

Area

Area

Area
Max

e
- tim
e
cl
Cy
Latency

Latency

Latency
Latency
Max

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 Pareto points

 Multi-criteria optimization

 Multiple objectives

 Pareto point:
A point of the design space is a Pareto point if there is no other point
with:
 At least one inferior objective
 All other objectives inferior or equal

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 Example
Differential equation solver

diffeq {
read ( x, y, u, dx, a ) ;
repeat {
xl = x + dx;
ul = u – ( 3 . x . u . dx ) – ( 3 . y . dx ) ;
yl = y + u . dx ;
c=x<a;
x = xl; u = ul; y = yl ;
until ( c );
write ( y )
}

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 Example

STEERING CONTROL
ALU
* & UNIT
MEMORY

STEERING CONTROL
ALU
* ALU
* &
MEMORY
UNIT

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 Example

Area

15
(2,2)
13 (2,1)
12

10

8 X(1,2)
7 (1,1)
5

Latency

1 2 3 4 5 6 7 8

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 Summary

 Computer-aided IC design methodology:

 Capture design by HDL models
 Synthesize more detailed abstractions
 Optimize circuit parameters

 Computer-aided system design methodology:

 Support for Hardware/Software co-design
 Synthesis of hardware, software and interfaces

 Evolving scientific discipline

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