Microprocessors 8085

What is Microprocessor ?
• Micro- 10-6
• Processor- Processes- works, has brain,
performs Arithmetic and logic instructions
• Any Examples from Day to Day life ?
• How is microprocessor different from
microcomputer ?
• Latest Processors?
 Microprocessor

Memory

Microprocessor

I/O Device or
Peripherals
 Buses For Communication

Address Control
Lines Data Lines Bus

• 16 bit for Memory • Single bit Line

• 8 bit lines
• 8 bit for Peripheral
 Basics of Microprocessor
• 8 bit processor
• 16 address lines, 8 data lines and a control
unit
• Memory and peripherals are separate
Three Major Elements

A.L.U.

Register Control
Array Unit
 Operation performed by up
• Microprocessor Initiated Operation
• Internal Data Operation
• Peripheral Initiated Operation
 Microprocessor Initiated Function
• Memory Read – Microprocessor reads from
memory
• Memory Write – Microprocessor writes in the
memory
• I/O Read- Microprocessor reads from
peripheral
• I/O Write- Microprocessor writes in the
peripheral
 Internal Data Operation

• Storing 8 bit data

• Performing Arithmetic and Logic operations
• Testing for condition
• Sequencing the execution of instruction
• Temporary storage of memory in stack
 Internal Data Operation
ACCUMULATOR (A) S Z X AC X P X CY

B C
D E
H L
PROGRAM COUNTER (PC)
STACK POINTER (SP)
 REGISTER ARRAY- Storing 8 bit data and
performing Arithmetic operations

• 8 bit registers- A, B, C, D, E, H & L

• Extended register pair- 16 bit:
BX ( B & C)
DX (D & E)
HX (H & L)
 Flag register

SIGN
ZERO AUXILIARY PARITY CARRY
CARRY
 SIGN FLAG
• Sign- It checks the MSB of a data.
• If MSB is 1, number is considered to be –ve, of
MSB is 0, number is considered to be +ve.
• If MSB of the number is 1, Sign flag also shows
1, if MSB of the number is 0, Sign flag also
shows 1
D7 D6 D5 D4 D3 D2 D1 D0

MSB
 Lets Try
What will be sign flag for the following
examples:
• Move 80H to Register B
• 45H+A8H
• 91H AND BCH
• 5AH-93H
 ZERO FLAG
• If the result after any operation is 0, zero flag would be
set to 1.
• If the result after any operation is non 0, zero flag would
be set to 0.

Lets try:
1. 56H-56H
2. 74H OR 3DH
 AUXILIARY FLAG
• If in any operation, there is a carry/borrow
from D3 to D4 bit, then AC flag is set to 1 else it
is 0. CARRY

D7 D6 D5 D4 D3 D2 D1 D0

BORROW
 Lets Try
What will be Auxiliary Flag for the following
examples:
• 98H+6BH
• C5H-53H
• 66H-AEH
 PARITY FLAG
• If after operation, the number of 1’s in answer
is even, parity flag is 1
• If after operation, the number of 1’s in answer
is odd, parity flag is 0

Lets try:
1. 84H+4FH
2. 97H XOR 43H
 CARRY FLAG
• If, there is any carry/borrow from D7 bit, carry
flag is set to 1 else it is 0.
CARRY

D7 D6 D5 D4 D3 D2 D1 D0

BORROW
 Let’s Try
What will be carry flag for the following
examples
 3BH+34H
 A5H+83H
 49H-B5H
 QUESTION TIME
What will be effect on all the flags for
following operations:
1. 18H+4EH
2. C2H-69H
3. A1H AND 5EH
4. 4EH-94H
5. 34H XOR 34H
 Program Counter
• Sequencing the execution of program
• 16 bit register
• Carriers the address that has to be executed
next
Program in memory ( To be Executed)
Address Data
3000H 25H
3001H 66H
3002H 78H
3003H BDH
3004H C4H
 Stack Pointer
• 16 bit register
• Points to the address of stack in memory
• Temporary storage of data in stack

Address Data
4000H 25H
Address 3FFFH
Data 66H
3FFEH 78H
3FFDH BDH
3FFCH C4H
EXTERNALLY INITIATED OPERATIONS

• RESET
• READY
• INTERUPT
• HOLD
 8085 PIN CONFIGURATION
HOLD
RESET

READY
INTERRUPTS
 RESET
• Suspends all the current running operations.
• Initializes program counter to 0000H.
• All process stop

PROGRAM COUNTER- 0000H

 READY
• Helps to synchronize a slow working
peripheral with fast working processor.
• Peripheral not ready sends
0 at ready pin
• Peripheral ready sends a 1
at ready pin

SLOW WORKING
MICROPROCESSOR
PERIPHERAL

READY PIN
INTERRUPTS- Interrupt the microprocessor in
its current working state

VECTORED NON-VECTORED
Address of the program to be Address of the program to be
executed already known to executed NOT known to
microprocessor microprocessor

• TRAP-RST • INTR
4.5 (RST0-RST7)
• RST 5.5
• RST 6.5
• RST 7.5
 INTERRUPTS

NON-MASKABLE MASKABLE
Request CANNOT be Request CAN be denied by
denied by microprocessor microprocessor

• TRAP-RST • RST 5.5

• RST 6.5
4.5
• RST 7.5
• INTR
 HOLD
• Peripheral requests the hold of buses from
microprocessor to manage its data.

Can I get
hold of
your buses

HOLD PIN
PERIPHERAL
MICROPROCESSOR
Hold Acknowledgment
pin
YES
 Pin Configuration
• SOD-Serial Out Data
• SID- Serial In Data

0
SID
PERIPHERAL
MICROPROCESSOR
S0D
1
 MULTIPLEXING OF BUSES

A15 A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

• Higher order bus • Lower order bus

• Works as • Works as address
address bus bus first, save the
address in latch
and then behaves
as data bus.
ALE- Address Latch Enable
 Status Lines
Status IO/M S1 S0 Output
Output code 0 1 1 Read=0
Fetch
Memory Read 0 1 0 Read=0

Memory Write 0 0 1 Write=0

I/O Read 1 1 0 Read=0
I/O Write 1 0 1 Write=0
Interrupt 1 1 1 INTA=0
Acknowledgeme
nt
Hault Z 0 0 RD=WR=Z
INTA=1
HOLD Z X X “
RESET Z X X “
Architecture
 Types of Addressing Modes
1. Immediate Addressing Mode-
Given operation performed immediately on the
given data

Example- MVI A, 45H

SUI 76H
ADI 99H
LXI B, 1234H
 Registered Addressing Mode
• Operation performed on the data in the
registers.
• Registers written in instruction

• Examples-
MOV B, C
ADD D
 Direct Addressing Mode
• The address from where data is to be taken is
mentioned directly

• Examples:
• LDA 5678H
• IN 56H
 Indirect Addressing Mode
• The address from which data has to be taken
is mentioned indirectly

Example-
• LDAX B
• MOV A, M
 Implicit Addressing Mode
• The instructions whose operation is fixed

XCHG
HLT
 Instruction Cycle
• Instruction Cycle- Time taken by instruction to
complete the execution of the particular
instruction
• Example- MVI A, 45H
• Instruction cycle has various machine cycles
• Machine cycle-Time required to complete an
operation of accessing the IO/Memory
• Example- Memory read, Memory write, I/O
read and I/O write.
 Machine cycle Sequence
Instruction- MVI A, 56H
OF
Microprocessor Memory

A Flag Register
C000H MVI A, 56 3E
C001H 56
B C

D E

H L
C000H
PC C001H
MR
SP
 LDA 5000H

OF
Microprocessor Memory
C000H LDA 5000H 3A
A
B
Flag Register
C
C001H 00 MR
C002H 50
D E
MR
H L

PC C000H
C001H
SP
5000 24

MR
 STAX B

OF
Microprocessor Memory

A 23H Flag Register C000H STAX B 02

B 70H C 00H
D E 7000H 23H
H L

PC C000H MW
SP
 IN 65H
Microprocessor Memory

C000H MVI A, 56 3E
A Flag Register
C001H 56
B C

D E

H L

C000H
PC C001H MR
SP
 Instructions
Instruction No. of Operation Mode Machine No. of T Effect on
bytes cycle states Flags
sequenc
e

1. MOV rd , rs 1 (rd ) Registe OF No flags

(rs ) red effected
2. MVI r, 8 bit 2 (r) 8 bit Immed OF, MR No effect
data data iate
3. LXI rp , 16 3 (rp ) 16 bit Immed OF, MR, No effect
bit data iate MR
data
4. LDA 16 bit 3 (A) Data Direct OF, MR, No effect
address present on MR, MR
given
memory
location
5. STA 16 bit 3 (A) Stored In Direct OF, MR, No effect
address given MR, MW
memory
location
 Instructions
Instructio No. of operation Mode M.C. seq Flags
n bytes
8. MOV r, 1 (r) Data written Indirect OF, MR No EFFECT
M in memory
location given
by HL register
pair
9. MOV 1 (r) Data written Indirect OF, MW No Effect
M, r on the
memory
location given
by HL register
pair
10.LDAX rp 1 (A) Indirect OF, MR No effect
Data written
in the
memory
location given
 Instructions
Instruction No. of Operation Mod M.C. No. of T Effect on
bytes e seq states Flags

11. STAX rp 1 (A) Data written onIndir OF, No effect

ect MW
the memory
location given
by register pair

12. ADD r 1 (A) Regi OF Flags will

(A)+(r) ster be
ed effected
according
to result

13. ADI 8 2 (A)+8 bit data (A) Imm OF, MR Flags will
bit data edia be
te effected
according
to result
Instructio No. of Operation Mode M.C. seq No. of T Effect on
n bytes states Flags

15. SUB r 1 (A)-(r) Registere OF Acc. To

(A) d result

16. SUI 8 2 (A)-(8 bit Immediat OF, MR Acc. To

bit data data) e result
17. SUB M 1 (A)-(8 bit(A) imIndirec OF, MR Acc. To
data in t result
memory
whose
address is
given by
HL register
pair)

18. ADC r 1 (A)+(r)+ Registere OF Acc. To

(CY) (A) d result
Instructio No. of Operation Mode M.C. no. T Effect on
n bytes sequence states flags
20. ADC M 1 (A)+(8 bit Indirect OF, MR 7T According
data in to the
memory result
whose
address is
given by
HL
register
pair.
(A)
21. SBI 8 2 (A)-(8 bit Immediate OF, MR According
bit data data)-(CY) to the
(A) result

22. SBB r 1 (A) – (r)- Registered OF According

(CY)-----(A) to the
result
 Machine Cycle sequence
• Every machine cycle has T states given as
follows:
• OF- 4T
• MR/MW/IOR/IOW-3T

• For example- MVI C, 23H

• M.C. Sequence: OF, MR
• No. of T states: 4T + 3T=7T
 Time taken by any instruction
• Crystal Frequency: 6MHz
• Clock Frequency: 3MHz
• Thus, time taken by instruction MVI C, 23H is
7T and can be evaluated as:

• 7T=7*(1/f)=7*(1/3MHz)=2.33us
 Let’s try for other instructions
• STA 2376H- OF, MR, MR, MW – 13T- 4.33US
• PCHL-OF-6T- 2us
• DCX H- OF- 6T-2us
• ADD M-OF, MR- 7T, 2.33us
• SUI 56H-
Timing Diagram
Timing diagram for Output code Fetch
Memory Read
Memory Write
Instruction No. of Operation Mode Machine No. of T Effect on
bytes cycle states Flags
sequenc
e

1. MOV rd , rs

2. MVI r, 8 bit
data
3. LXI rp , 16 bit
data
4. LDA 16 bit
address

5. STA 16 bit
address
Instructio No. of operation Mode M.C. seq T- Flags
n bytes states
8. MOV r,
M

9. MOV
M, r

10.LDAX rp
Instruction No. of Operation Mod M.C. No. of T Effect on
bytes e seq states Flags

11. STAX rp

12. ADD r

13. ADI 8
bit data

14. ADD M
Instruction No. of Operation Mode M.C. seq No. of T Effect on
bytes states Flags

15. SUB r

16. SUI 8
bit data

17. SUB M

18. ADC r

19. ACI 8
bit data
Instructio No. of Operation Mode M.C. no. T Effect on
n bytes sequence states flags
20. ADC M

21. SBI 8
bit data

22. SBB r

23. SBB M
24. INR r

25. DCR r

26. MVI
M, 8 BIT
DATA
Instruction No. of Operation Mod M.C. No. of T Effect on
bytes e seq states Flags

INR M

DCR M

IN 8 BIT
port
address

OUT 8 port
address

INX rp
Instruction No. of Operation Mod M.C. No. of T Effect on
bytes e seq states Flags

DCX rp

ANA r

ANI 8 bit
data

ANA M
Instructio No. of Operation Mode M.C. no. T Effect on
n bytes sequence states flags
ORA r

ORI 8 bit
data

ORA M

XRA r
XRI 8 bit
data
XRA M
Instructio No. of Operation Mode M.C. no. T Effect on
n bytes sequence states flags
CMP r

CPI 8 bit
data

CMP M

RLC
RRC

RAL

RAR
Instructio No. of Operation Mode M.C. no. T Effect on
n bytes sequenc states flags
e
CMA

`CMC

NOP

STC
LHLD 16
bit
address
SHLD 16
bit
address
SPHL
Instructio No. of Operation Mode M.C. no. T Effect on
n bytes sequence states flags
PCHL

DAD rp

JMP 16 bit
address

JX 16 bit
address
DAA

HLT

XCHG