Unit 5

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Physical Design

UNIT:5
• Introduction to ECAD tools for front and back
end design of VLSI circuits.
• Design using FPGA and VHDL. VHDL Code for
simple Logic gates, flip-flops, shift registers.
• Custom /ASIC design.
ECAD tools
• Electronic design automation (EDA), also
referred to as electronic computer-aided
design (ECAD), is a category of software tools
for designing electronic systems such as
integrated circuits and printed circuit boards.
• ECAD (electronic computer-aided design)
software is used to design and create
electronic structures.
Introduction to ECAD tools for front and back end design of VLSI
circuits

• Front-end design is concerned with the


functional specification of the system, while
back-end design focuses on the physical
implementation of the design.
• Front-end design is typically done using high-
level design languages, while back-end design
uses specialized CAD tools and algorithms.
Back end Design
• On the Back end Design, engineers can start with
logic synthesis, Placement and Routing , Layout,
Physical verification, static timing analysis. Most of
the back end engineers would need a better
understanding of process technologies, transistors,
high speed design issues and a good grasp of tools
and automation.
• All stages from Logic Synthesis till Fabrication are
considered as back end and engineers working on
any of these are considered as Back end VLSI design
VHDL Code for simple Logic gates, flip-flops,
shift registers
• VHDL is a short form of VHSlC Hardware
Description Language where VHSIC stands for
Very High Speed Integrated Circuits.
• It's a hardware description language – means
it describes the behavior of a digital circuit,
and also it can be used to derive or implement
a digital circuit/system hardware.
VHDL Introduction

• VHDL stands for very high-speed integrated


circuit hardware description language.
• It is a programming language used to model a
digital system by dataflow, behavioral and
structural style of modeling.
• This language was first introduced in 1981 for
the department of Defense (DoD) under the
VHSIC program.
Describing a Design

• Entity declaration

• Architecture
VHDL code for the basic gates-
AND, OR, OT, NAND, NOR, XOR, XNOR
VHDL Code For The Half Adder
VHDL Code For The Full Adder
VHDL Code For SR Flip-flop
end process;
end ff;
VHDL for JK flip-flop
VHDL for D flip-flop
VHDL for T flip-flop
VHDL for shift registers
VHDL for implementing the
• Serial In Serial Out(SISO) and
• Serial In Parallel Out(SIPO) shift registers
using single entity and multiple architectures
VHDL For Shift Register
VHDL code for implementing the
Parallel In Serial Out shift register(PISO)
VHDL For Shift Register
VHDL for implementing
• the Parallel In Parallel Out shift register(PIPO).
Custom /ASIC design
• ASIC [“a-sick”] is an acronym for Application
Specific Integrated Circuit.
• As the name indicates, ASIC is a non-standard
integrated circuit that is designed for a specific
use or application.
• Generally an ASIC design will be undertaken for a
product that will have a large production run ,
and the ASIC may contain a very large part of the
electronics needed on a single integrated circuit.
Asics Are Broadly Classified Into Three
Types.
• I. Full-Custom ASICs

• II. Semi-custom ASICs

• III. Programmable ASICs


Full-Custom ASICs
• A Full custom ASIC is one which includes some (possibly
all) logic cells that are customized and all mask layers that
are customized.
• A microprocessor is an example of a full-custom IC .
Designers spend many hours squeezing the most out of every
last square micron of microprocessor chip space by hand.
• Customizing all of the IC features in this way allows
designers to include analog circuits, optimized memory cells,
or mechanical structures on an IC, for example. Full-custom
ICs are the most expensive to manufacture and to design.
• In a full-custom ASIC an engineer designs
some or all of the logic cells, circuits, or layout
specifically for one ASIC. This means the
designer avoids using pretested and pre
characterized cells for all or part of that
design.
Semicustom ASICs
• ASICs , for which all of the logic cells are
predesigned and some (possibly all) of the mask
layers are customized are called semi custom
ASICs.
• Using the predesigned cells from a cell library
makes the design , much easier.
• There are two types of semicustom ASICs
(i) Standard-cell–based ASICs
(ii)Gate-array–based ASICs.
(i) Standard-Cell Based ASICs
• A cell-based ASIC (cell-based IC, or CBIC
pronounced sea-bick) uses predesigned logic
cells (AND gates, OR gates, multiplexers, and
flip-flops, for example) known as standard
cells.
• One can apply the term CBIC to any IC that
uses cells, but it is generally accepted that a
cell-based ASIC or CBIC means a standard-cell
based ASIC.
(i) Standard-Cell Based ASICs
• The standard-cell areas (also called flexible blocks)
in a CBIC are built of rows of standard cells like a
wall built of bricks. The standard-cell areas may be
used in combination with microcontrollers or even
microprocessors, known as mega cells.
• Mega cells are also called mega functions, full-
custom blocks, system-level macros (SLMs), fixed
blocks, cores, or Functional Standard Blocks (FSBs).
The ASIC designer defines only the placement of the standard cells
and the interconnect in a CBIC. However, the standard cells can be
placed anywhere on the silicon; this means that all the mask layers of
a CBIC are customized and are unique to a particular customer.

• The advantage of CBICs is that designers save time, money, and


reduce risk by using a predesigned, pretested, and pre characterized
standard-cell library.

• In addition each standard cell can be optimized individually.


During the design of the cell library each and every transistor in
every standard cell can be chosen to maximize speed or minimize
area .
•The disadvantages are the time or expense of designing or buying
the standard-cell library and the time needed to fabricate all layers of
the ASIC for each new design.
(ii)Gate-Array–Based Asics
• In a gate array (sometimes abbreviated GA) or
gate-array based ASIC the transistors are
predefined on the silicon wafer.
• The predefined pattern of transistors on a gate
array is the base array , and the smallest
element that is replicated to make the base
array is the base cell (sometimes called a
primitive cell )
(ii)Gate-Array–Based Asics
• Only the top few layers of metal, which define
the interconnect between transistors, are
defined by the designer using custom masks.
To distinguish this type of gate array from
other types of gate array, it is often called a
masked gate array ( MGA ).
• • The designer chooses from a gate-array
library of predesigned and pre-characterized
logic cells.
• The logic cells in a gate-array library are often
called macros . The reason for this is that the
base-cell layout is the same for each logic cell,
and only the interconnect (inside cells and
between cells) is customized, which is similar to a
software macro.
• Types of MGA or Gate-array based ASICs
• There are three types of Gate Array based ASICs.
1. Channeled gate arrays.
2. Channelless gate arrays.
3. Structured gate arrays.
III. Programmable ASICs
• Programmable logic devices ( PLDs ) are
standard ICs that are available in standard
configurations.
• However, PLDs may be configured or
programmed to create a part customized to a
specific application, and so they also belong to
the family of ASICs.
• PLDs use different technologies to allow
programming of the device.
Features of PLDs
• No customized mask layers or logic cells.
• Fast design turnaround.
• A single large block of programmable
interconnect .
• A matrix of logic macro cells that usually
consist of programmable array logic followed
by a flip-flop or latch.
Features of PLDs
• The simplest type of programmable IC is a
read-only memory( ROM ). The most common
types of ROM use a metal fuse that can be
blown permanently (a programmable ROM or
PROM ).
• An electrically programmable ROM , or EPROM
, uses programmable MOS transistors whose
characteristics are altered by applying a high
voltage.
Features of PLDs
• One can erase an EPROM either by using another
high voltage (an electrically erasable PROM , or
EEPROM ) or by exposing the device to ultraviolet
light (UV-erasable PROM, or UVPROM).
• • There is another type of ROM that can be placed
on any ASIC a mask-programmable ROM (mask-
programmed ROM or masked ROM).
• A masked ROM is a regular array of transistors
permanently programmed using custom mask
patterns.
Field-Programmable Gate Arrays(FPGAs)

• FPGAs are the newest member of the ASIC family


and are rapidly growing in , replacing TTL in
microelectronic systems. Even though an FPGA is a
type of gate array, we do not consider the term gate-
array based ASICs to include FPGAs.
• • There is very little difference between an FPGA
and a PLD .An FPGA is usually just larger and more
complex than a PLD. In fact, some vendors that
manufacture programmable ASICs call their products
as FPGAs and some call them as complex PLDs .
Characteristics of an FPGA
• None of the mask layers are customized.
• There is a method for programming the basic logic
cells and the interconnect.
• The core is a regular array of programmable basic
logic cells that can implement combinational as well as
sequential logic (flip-flops).
• A matrix of programmable interconnect surrounds
the basic logic cells.
• Programmable I/O cells surround the core.
• Design turnaround is a few hours.
FPGA

• The architecture consists of configurable logic


blocks, configurable I/O blocks, and
programmable interconnect.
• Also, there will be clock circuitry for driving the
clock signals to each logic block, and additional
logic resources such as ALUs, memory, and
decoders may be available.
• The two basic types of programmable elements
for an FPGA are Static RAM and anti-fuses.

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