1

CHAPTER ONE

DIGITAL LOGIC AND

DIGITAL SYSTEMS

12/10/2023 CA_OS- CH1 – Digital Logic and Digital Systems

 CH-1 Contents
2

1. Overview of Computer Organization and

Architecture
2. Logic gates and Boolean Algebra
3. Combinational and Sequential Circuits
4. Programmable Logic Devices
5. Machine level representation of data

12/10/2023
 CH-1 Contents
3

1. Overview of Computer Organization and

Architecture
2. Logic gates and Boolean Algebra
3. Combinational and Sequential Circuits
4. Programmable Logic Devices
5. Machine level representation of data

12/10/2023
 Overview of Computer Organization and
Architecture
4

 Key Terms
 Signal
 Analog Signal vs Digital Signal
 Analog System vs Digital System

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 Digital Computer : is a digital system that perform

various computational tasks.
 Digital: implies that the information in the computer is
represented by variables that take a limited number of
discrete values.
 Digital computers use the binary number system,
which has two digits: 1 and 0.
 A binary digit is called a BIT.
 Information is represented in digital computers in groups of
bits.

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 Organization of a digital computer

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 Computer system: is subdivided into two

functional entities: Hardware and Software.
 Hardware: consists of all the electronic components
and electromechanical devices that comprise the
physical entity of the device.
 Software: consists of the instructions and data that
the computer manipulates to perform various data-
processing tasks.
 A sequence of instructions for the computer is called a
program. The data that are manipulated by the program
constitute the database.
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 Computer Architecture
 Logical aspects of a computer system
 Focuses on the structure and behavior of a computer
system
 It is operational attributes are linked together and to realize
the architectural specifications
 What the computer does?
 Example: instruction set and format, the number of
bits used to represent different data types, I/O
mechanisms, and techniques for addressing memory.

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 Computer Organization
 Physical aspect of a computer system
 It concerned with the way the hardware are
connected together to form the computer system
 Study on how various circuits and components fit together
to create a working computer
 How the computer does it?
 Example: circuit design, control signal, interface
between the computer and peripherals, and the
memory technology used

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 Why study COA?

 Design better programs
 Including system software such as compiler, operating
system, and device drivers
 Optimize program behavior
 Evaluate (benchmark) computer system performance
 Understand time, space, and price tradeoffs

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 CH-1 Contents
12

1. Overview of Computer Organization and

Architecture
2. Logic gates and Boolean Algebra
3. Combinational and Sequential Circuits
4. Programmable Logic Devices
5. Machine level representation of data

12/10/2023
 Logic gates and Boolean Algebra
13

 Signal: a physical quantity, which contains some

information.
 Signals are of 2 types analog and digital
 A particular digital computer may employ
 3 volts to represent binary 1 and
 0.5 volts to represent binary 0.

 Logic gates are the basic building blocks of any

digital system.
 It is an electric circuit having one or more than one
input and only one output.
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 The relationship between the input and the output

is based on a certain logic.
 A useful way of describing the relationship between
the inputs of gates and their output is the truth table.
 In a truth table, the value of each output is tabulated
for every possible combination of the input values.
 We usually consider three basic kinds of gates,
 AND gate
 OR gate
 NOT gate (inverter)
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 Applications of the 3 basic gates

 The logic gates are the building blocks for all
computers, smart phones and the whole internet. Here
is some day to day applications of the 3 basic gates,
that a common person may relate to:
 AND Gate
 OR Gate
 NOT Gate

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 AND Gate

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 OR Gate

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 NOT Gate

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 Combined Gates
 It is practical to combine functions of the basic gates
into more complex gates, (for instance in order to save
space in circuit diagrams).
 There are four combined gates
 NAND gate
 NOR gate
 XOR gate
 XNOR gate

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 Boolean algebra
23

 Boolean algebra is an algebra that deals with

binary variables and logic operations.
 It is used to analyze and simplify the digital (Logic)
circuits.
 It uses only the binary numbers i.e. 0 and 1. It is
also called as Binary Algebra or logical Algebra.
 Boolean algebra was invented by George Boole in
1854.

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 Rule in Boolean algebra

 Variable used have only two values.
 Binary 1 for HIGH and Binary 0 for LOW
 Complement of a variable is represented by an overbar or single
quotation (-/’).
 Thus, complement of variable B is represented as B’. thus if B=0 then
B’=1 and B=1 and B’=0
 ORing of the variables is represented by a plus (+) sign between
them.
 For example ORing of A, B, C is represented as A + B + C
 Logical ANDing of the two or more variable is represented by
writing a dot between them such as A.B.C.
 Sometimes the dot may be omitted like ABC.
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 Boolean Function can be expressed algebraically with

 Binary variables, The logic operation symbols, Parenthesis,
and Equal sign.
 The Boolean function can be either 1 or 0.
 F= x+y’z
 The relationship between a function and its binary
variables can be represented in a truth table.
 To represent a function in a truth table we need a list of
the 2n combinations of the binary variables.
 F= x + y’z ….. there are eight(23) possible distinct
combinations for assigning bits to the three variables x, y, and
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 A Boolean function can be transformed from an

algebraic expression into a logic diagram composed of
AND, OR, and NOT(inverter) gates.
 The purpose of Boolean algebra is to facilitate the
analysis and deign of digital circuits.
 To provides a convenient tools to :
1. Express in algebraic form a truth table relationship
between binary variables
2. Express in algebraic form the input-output relationship
of logic diagrams
3. Find simpler circuits for the same function
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 Example-1
27

 F= x+y’z
a) Represent the above function using truth table
b) Draw the logical diagram

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 Exercise-1
29

1. F= (B+C)+(AB)’(A’ +C)’
a) Represent the above function using truth table
b) Draw the logical diagram
2. F= A’C + AB’C + ABC’
a) Represent the above function using truth table
b) Draw the logical diagram
3. F= AB’C’D + A’BCD’
a) Represent the above function using truth table
b) Draw the logical diagram
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 Exercise-2
Write the algebraic function?
30

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 Boolean Laws
31

 AND law: these laws use the AND operation. Therefore

they are called as AND laws
1. A.0 = 0
2. A.A = A
3. A.1 = A
4. A.A’ = 0
 OR law: these laws use the OR operation. Therefore they
are called as OR laws
5. A+0 =A
6. A+A=A
7. A+1 =1
8. A + A’ = 1
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 Commutative law: any binary operation which

satisfies the following expression.
9. A.B = B.A
10. A+B =B +A
 Commutative law states that changing the sequence
of the variables does not have any effect on the
output of logic circuits.

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 Associative law: states that the order in which the

logic operations are performed is irrelevant s their
effect is the same
11. (A.B).C = A.(B.C)
12. (A + B ) + C = A + (B + C)
 Distributive law: states the following condition
13. A.( B + C) = A.B + A.C
14. A+( B . C) = (A+B) . (A+C)

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 Inversion law: this law uses the not operation. The

inversion law states that double inversion of a
variable results in the original variables itself.
15. A’’ = A
 DeMorgan’s Theorem
 Very important in dealing with NOR and NAND gates.
16. (A.B)’ = A’ + B’
17. (A + B)’ = A’.B’

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 From the general DeMorgan's theorem we can

derive a simple procedure for obtaining the
complement of an algebraic expression. This is
done
1. By changing all OR operations to AND operations
and a AND operations to OR operations and then
2. Complementing each individual letter variable.
 Example
 F= AB + C’D’ + B’D
 F’=(A’ + B’)(C + D)(B + D’)
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 NOR and NAND
36

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 Simplifying Boolean functions
37

1. Minimization by Boolean Algebra

1. Grouping
2. Multiplication by redundant variables
3. Application of DeMorgan’s Theorem
2. Minimization by Karnaugh Maps (K-Map)

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 Example-2
38

 Simplify using Boolean Algebra Method

1. B+AB’C’D
2. AB +(AB)CD’

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 Solution : Example-2
39

 B + AB’C’D  Rules and Laws

 (B+A)(B+B’)(B+C’)(B+D)  Distributive law
 (B+A) (B+C’)(B+D)  OR Law

 B + AC’D  Common factor: grouping

 AB + (AB)CD’  Rules and Laws

 (AB+AB)(AB+CD’)  Distributive law
 AB+CD’  OR Law

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 Exercise-3:
Simplify using Boolean Algebra
40

1. (X+Y) +(X+Y)Z
2. AB’(AB’ +B’C)
3. AB’C + B’
4. B+AB’C’D
5. Y’(X+Y+Z)
6. (X+Y)((X+Y)’+Z)
7. AB +(AB)’CD’
8. ABC +AB’C
9. (AD+B+C)(AD+(B+C)’)
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 Minimization by Boolean Algebra: Limitation

 The truth table representation of a function is unique,
but the function can appear in many different forms
when expressed algebraically.
 The expression may be simplified using the basic
relations of Boolean algebra. However, this procedure
is sometimes difficult because
 It lacks specific rules for predicting each succeeding step
in the manipulative process.

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 Minimization by Karnaugh Maps (K-Map)

(Map Simplification)
 The complexity of the logic diagram that
implements a Boolean function is related directly to
the complexity of the algebraic expression from
which the function is implemented.
 Example
 Draw the logic diagram for the given function
 F= X’Y’Z + XYZ’ + XYZ + XY’Z’ + XY’Z

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 Form of Boolean Expression

 Sum of products form (SOP )
 First the product(AND) terms are formed then these are
summed(OR)
 E.g. ABC+DEF+GHI
 Product of sum form(POS)
 First sum(OR) terms are formed then the products are
taken(AND)
 E.g. (A+B+C)(D+E+F)(G+H+I)

 It is possible to convert between these two forms

using Boolean algebra (De-Morgan’s)
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 Minterms and Maxterms

 MINTERM
 For a function of n variables, if a product term contains each of
the n variables exactly one time in complemented or un-
complemented form, the product term is called a MINTERM.
 If the function is represented as a sum of min-terms only, the
function is said to be in canonical sum of products (canonical
SOP) form.
 For example,
 fi(A, B, C)= A’BC’ + ABC’ +A’BC+ABC
 A special notation is commonly used in which each
minterm is represented by an n-bit binary code
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 Each bit represents one of the variables of the

minterm as follows;
 Un-complemented variables: 1
 Complemented variables: 0
Min-term Minterm Minterm
 fi(A, B, C),= m2+m3+m6+m7 code number
 fi(A, B, C)= ∑m(2,3,6,7) A’BC’ 010 m2

ABC’ 110 m6

A’BC 011 m3

ABC 111 m7
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 MAXTERMS
 If a sum term of a function of n variables contains each of
the n variables exactly one time in complemented or
uncomplemented form, the sum term is called a
MAXTERM.
 If a function is represented as a product of sum terms, each
of which is a maxterm, the function is said to be in
canonical product of sum (canonical POS) form.
 For example
 fi(A, B, C)= (A+B+C) (A+B+C’) (A’+B+C)(A’+B+C’)

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 Each bit represents one of the variables of the

minterm as follows;
 Un-complemented variables: 0
 Complemented variables: 1 Maxterm Maxterm Maxterm
 fi(A, B, C) = M0.M1.M4.M5 code number
A+B+C 000 M0

fi(A, B, C) = πM(0,1,4,5) A+B+C’ 001 M1

A’+B+C 100 M4

A’+B+C’ 101 M5
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 Exercises-4
48

 Given the function

f(A, B, C)= (A+B+C’) (A+B’+C’) (A’+B+C’)
(A’+B’+C’)
1. Construct the truth table and
2. Express the function in both maxterm and minterm
form.

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 Canonical form
 There are two form of Boolean expression: SOP and
POS.
 Boolean function can be expressed as Canonical Form
 The canonical form of a boolean function is unique, which
means that there is only one possible canonical form for a
given function.
 The canonical form of a boolean function provides a clear
and unambiguous representation of the function
 The canonical form of a boolean function can represent any
possible boolean function, regardless of its complexity.
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 Canonical form is not efficient but sometimes useful in

analysis and design
 It can be complex, especially for functions with many variables.
 It can be computationally expensive, especially for large
functions
 It can be redundant , which means that it can contain
unnecessary terms or variables
 In an expression in canonical form, every variable
appears in every term
 f(A,B,C,D)= ABC’D +AB’CD +AB’CD’
 Note that the dot(meaning AND) is often omitted.

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 Derivation of Canonical Forms

 A SOP expression can be forced into canonical form
by ANDing the incomplete terms with terms of the
form (X+X’) where X is the name of the missing
variable.
 E.g. f(A,B,C) =AB+BC
=AB(C+C’) + BC (A+A’)
=ABC + ABC’ + ABC +A’BC
=ABC+ ABC’ + A’BC

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 A POS expression can be forced into canonical form

by ORing the incomplete terms with terms of the form
(A+ (X.X’)) where X is the name of the missing
variable and A is the terms contain missed variable .
 E.g. f(A,B,C) =(A+B+C)(A+B)
 A+B=(A+B)+(C.C’)=(A+B+C).(A+B+C’)
f(A,B,C) =(A+B+C) (A+B+C)(A+B+C’)
f(A,B,C) =(A+B+C)(A+B+C’)

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 Exercise-5
53

1. Convert the following function to canonical SOP

form
f(A,B,C) = AB+ AC’ + A’C
2. Convert the following function to canonical POS
form
f(A,B,C) = A(A+C’)

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 Karnaugh map or K-map
54

 The map method provides a simple, straight forward

procedure for simplifying Boolean expressions.
 This method may be regarded as a pictorial
arrangement of the truth table which allows an
easy interpretation for choosing the minimum
number of terms needed to express the function
algebraically.
 The map method is also known as the Karnaugh
map or K-map.

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 The map is a diagram consisting of squares.

 For n variables on a K-map there are 2n numbers of
squares.
 Each square or cell represents one of the minterms.
 Since any Boolean function can be expressed as a sum of
MINTERMS.
 It is possible to recognize a Boolean function
graphically in the map from the area enclosed by those
squares whose minterms appear in the function.

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 Minimization by K - Maps
 A grid of squares, each square represents one minterm.
The minterms are ordered according to Gray Code
(00, 01, 11,10)
 Only one variable changes between adjacent squares
 Squares on edges are considered adjacent to squares on
opposite edges

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 Filling out a K-Map

 Write the Boolean expression in SOP form
 For each product term, write a 1 in all the squares
which are included in the term, 0 elsewhere

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 Example-3
59

 Let us plot the following function on K-map

 f(a,b,Q,G)= m(0,3,5,7,10,11,12,13,14,15)

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 Exercise-6
60

 Consider the following function, which is

expressed as a sum of products. Plot the given
function on K-map
 f(A,B,C)= AB + BC’

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 Rules of K-map Simplification
61

1. No zeros allowed
2. No diagonals
3. Only power of 2 number of cells in each group
4. Groups should be as large as possible
5. Every one must be in at least one group
6. Overlapping allowed
7. Wrap around allowed
8. Fewest number of groups possible

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 Minimization techniques
67

 Minimization is done by spotting patterns of 1’s

and 0’s
 Simple theorems are then used to simplify the
Boolean description of the patterns.
 Pairs of adjacent 1’s
 Remember that adjacent squares differ by only one
variable
 Hence the combination of 2 adjacent squares has the
form P(A+A’)
 This can be simplified (from before) too just P
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 The adjacent squares ABC and A’BC differ only in

A
 Hence they can be combined into just BC

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 Example-4: Simplification using K-Map
71

 Find the simplest switching expression for the

given function using K-Map.
 F(A,B,C) = A’B’C + A’BC + AB’C + ABC +ABC’

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 Step to simplify using K-Map
72
1
1. Identify Important Information
 Identify the number of variables
 Writing the Boolean expression in SOP form
 Identify the MINTERMs from the given function
 Number of variable
 Three (3) … A, B and C

 List of MINTERMs
Min-term Minterm code Minterm number
A’B’C 001 m1
A’BC 011 m3
AB’C 101 m5
ABC 111 m7
ABC’ 110 m6
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 Step to simplify using K-Map
73
2
2. Draw the Map
 Identify the number of squares
 Row x Column
 Assign codes for Rows and Columns
 N.B. follow the order of the variable in the given function

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 Step to simplify using K-Map
74
3
3. Filling out the K-Map
 For each MINTERM, write a 1 in all the squares which
are included in the terms list, 0 elsewhere

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 Step to simplify using K-Map
75
4
4. Selecting adjacent squares
 Number of selected squares should be SQUARE of 2
 Maximum number of squares

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 Step to simplify using K-Map
76
5
5. Simplify each selected squares
 Moving on the left side & top side and simplify
 ANDing the left side & top side simplified expression
 ORing each result
 From the RED (4 adjacent squares)
 C

 From the BLUE (2 adjacent squares)

 AB

 The simplified expression is

 C + AB

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 Exercise-7: Simplification using K-Map
77

 Find the simplest switching expression for the

given function using K-Map.
1. f(A,B,C)= ∑m(1,4,5)
2. f(A,B,C)= ΠM(1,3,5,7)

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 CH-1 Contents
78

1. Overview of Computer Organization and

Architecture
2. Logic gates and Boolean Algebra
3. Combinational and Sequential Circuits
4. Programmable Logic Devices
5. Machine level representation of data

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 Combinational and Sequential Circuits
79

 Circuit Designing is a process of designing for use

our device how to make it perfect in processing
speed, working, portable, space consumer, feed
back, reliability, good efficiency and space
consumer.
 Their are two types of circuit in circuit designing
1. Combinational Circuits
2. Sequential Circuits
 Practical computer circuits normally contain a
mixture of combinational and sequential circuits.
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 Combinational Circuits
 When logic gates are connected together to produce a
specified output for certain specified combination of the
input variable, with no storage involved, the resulting
circuit is called a combinational logic circuits
(combinational circuits).
 Combinational Logic Circuits are classified into three
major parts as
 Arithmetic and Logic functions,
 Date transmission
 Code converters

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 Some of the characteristics of combinational circuits

are following:
1. The output of combinational circuit at any instant of
time, depends only on the levels present at input
terminals.
2. The combinational circuits do not use any memory.
 The previous state of input does not have any effect on the
present state of the circuit.
3. A combinational circuit can have an ‘n’ number of
inputs and ‘m’ number of outputs.

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 Function : Combinational Circuit

 The three main ways of specifying the function of a
combinational logic circuit are:
 Boolean Algebra
 This forms the algebraic expression showing the operation of the logic
circuit for each input variable either True or False that results in a logic “1”
output.
 Truth Table
 A truth table defines the function of a logic gate by providing a concise list
that shows all the output states in tabular form for each possible
combination of input variable that the gate could encounter.
 Logic Diagram
 This is a graphical representation of a logic circuit that shows the wiring
and connections of each individual logic gate, represented by a specific
graphical symbol, that implements the logic circuits.
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 Design Steps: Combinational circuits

 The design of combinational circuits starts from the
verbal outline of the problem and ends in a logic
circuit diagram. The procedure involves the
following steps:
1. Understand the problem
2. Assign letter symbol for the input and output variables
3. Construct the truth table that defines the relationship
between inputs and outputs
4. Obtain the simplified Boolean functions for each output
5. Draw the logic diagram
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 Sequential Circuits
 When the output of a circuit depends on the present input and
past output then these logic are termed as Sequential logics
and respective circuits are known as Sequential circuits.
 This requires a memory element in order to store the past
output.
 Sequential Logic Circuits are classified into three major parts
as
 Event driven,
 Clock drive
 Pulse driven

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 Latches and flip-flops

 The logic circuits discussed previously are known as
combinational, in that the output depends only on the
condition of the latest inputs
 However, there is a type of logic where the output
depends not only on the latest inputs, but also on the
condition of earlier inputs.
 These circuits are known as sequential, and implicitly they
contain memory elements.

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 Memory Elements
 A memory stores data – usually one bit per element
 A snapshot of the memory is called the state
 A one bit memory is often called a bi-stable, i.e., it has 2
stable internal states
 Latches and Flip-flops are particular implementations of
bi-stables

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 Both Latches and flip flops are circuit elements

wherein the output not only depends on the current
inputs, but also depends on the previous input and
outputs.
 The main difference between the latch and flip
flop is that a flip flop has a clock signal, whereas
a latch does not.
 There are basically four main types of latches and flip-
flops: SR, D, JK, and T.

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 Flip-Flops
 The storage elements employed in clocked sequential
circuits are called flip-flops.
 A flip-flop is a binary cell capable of storing one bit of
information.
 It has two outputs, one for the normal value and one for
the complement value of the bit stored in it.
 A flip-flop maintains a binary state until directed by a clock
pulse to switch states.

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 The difference among various types of flip-flops is in

the number of inputs they possess and in the manner
in which the inputs affect the binary state.
 The most common types of flip-flops are presented
below.
 SR Flip-Flop
 D Flip-Flop
 JK Flip-Flop
 T Flip-Flop

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 Design Steps: Sequential circuits

1. Understand the circuit and write circuit specification
2. Translating the circuit specifications into a state
diagram.
3. Convert the state diagram into a state table.
4. Extend the state table into an excitation table
5. Find the set of flip-flop input equation for the
combinational circuit
6. Draw the logic diagram
 Read more: https://
bob.cs.sonoma.edu/IntroCompOrg-RPi/sec-seqdes.html
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 Integrated Circuit (IC)
95

 An IC is a small silicon semi-conductor crystal,

called a chip, containing the electronic components
for the digital gates.
 Digital circuits are constructed with integrated
Circuits.
 The various gates a interconnected inside the chip to
form the required circuit.
 As the technology of ICs improved, the number of
gate that can be put in a single chip has increased
considerably.
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 Classification of IC based on logical operation

 Small Scale Integration (SSI)
 The number of gates usually less than 10 and is limited by the number
of pins available in the PC.
 Medium Scale Integration (MSI)
 Have a complexity approximately 10 – 200 gates
 Decoder, adder and register
 Large Scale Integration (LSI)
 Contain between 200 and a few thousands
 Processor, memory chip and programmable module
 Very Large Scale Integration (VLSI)
 Contain thousands of gates
 Large memory array, complex microcomputer chips
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 Application of IC
 Timers
 Counters
 Multiplexers
 Calculator chips
 Memory chips
 Clock chips
 Microprocessor
 Microcontroller
 Temperature chips…
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 CH-1 Contents
98

1. Overview of Computer Organization and

Architecture
2. Logic gates and Boolean Algebra
3. Combinational and Sequential Circuits
4. Programmable Logic Devices
5. Machine level representation of data

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99

 Increasing levels of integration made it possible to put

more gates on a chip and to make gate interconnections
on the chip as well. This yields the advantages of
 Decreased cost,
 Decreased size, and
 Increased speed
 A design problem arises, however. For each particular
logic function or set of functions, the layout of gates
and interconnections on the chip must be designed.
 The cost and time involved in such custom chip design is
high.
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 Thus, it becomes attractive to develop a general-

purpose chip that can be readily adapted to
specific purposes.
 This is the intent of the programmable logic device
(PLD).
 PLD refers to any type of integrated circuit used
for implementing digital hardware, where the chip
can be configured by the end user to realize
different designs.

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 Programmable Logic Devices (PLDs) : are the

integrated circuits.
 They contain an array of AND gates & another array
of OR gates.
 There are three kinds of PLDs based on the type of
arrays, which has programmable feature.
1. Programmable Read Only Memory
2. Programmable Array Logic
3. Programmable Logic Array

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 The process of entering the information into these

devices is known as programming.
 Basically, users can program these devices or ICs
electrically in order to implement the Boolean
functions based on the requirement.
 Programming of such a device often involves placing
the chip into a special programming unit.
 Here, the term programming refers to hardware
programming but not software programming.

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 Programmable Read Only Memory PROM

 Read Only Memory (ROM) is a memory device,
which stores the binary information permanently.
 That means, we can’t change that stored information by any
means later. If the ROM has programmable feature, then it
is called as Programmable ROM (PROM)
 The user has the flexibility to program the binary
information electrically once by using PROM programmer.
 PROM is a programmable logic device that has fixed
AND array & Programmable OR array.

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 Programmable Array Logic (PAL)

 PAL is a programmable logic device that has
Programmable AND array & fixed OR array.
 The advantage of PAL is that we can generate only the
required product terms of Boolean function instead of
generating all the min terms by using programmable
AND gates.

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 Programmable Logic Array (PLA)

 PLA is a programmable logic device that has both
Programmable AND array & Programmable OR array.
Hence, it is the most flexible PLD.

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 CH-1 Contents
109

1. Overview of Computer Organization and

Architecture
2. Logic gates and Boolean Algebra
3. Combinational and Sequential Circuits
4. Programmable Logic Devices
5. Machine level representation of data

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 Machine level representation of data
110

 Data and instructions cannot be entered and

processed directly into computers using human
language.
 Computers not only process numbers, letters and special
symbols but also complex types of data such as sound
and pictures.
 However, these complex types of data take a lot of memory and
processor time when coded in binary form.
 Binary information in digital computers is stored in
memory or processor-registers.
 Register contain either data or control information.
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 The data types found in the registers of digital

computers are
1. Numbers used in arithmetic computations
2. Letters of the alphabet used in data processing
3. Other discrete symbols used in specific purpose
 All types of data, except binary numbers, are
represented in computer registers in binary coded
form.

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 The Alphanumeric Representation

 The data entered as characters, number digits, and
punctuation are known as alphanumeric data.
 Three (3) alphanumeric codes are in common use.
 ASCII (American Standard Code for Information
Interchange)
 Unicode
 EBCDIC (Extended Binary Coded Decimal Interchange
Code).

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 The Decimal Representation

 BCD (Binary Coded Decimal) is often used to
represent decimal number in binary.

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 Fixed point number representation

 Computers use a fixed number of bits to represent an
integer. The commonly-used bit-lengths for integers
are 8-bit, 16-bit, 32-bit or 64-bit.
 Besides bit-lengths, there are two representation
schemes for integers:
1. Unsigned integers (0 and +VE integers)
2. Signed integers (0 , -VE and +VE integers)
A. Sign-Magnitude representation
B. 1’s complement representation
C. 2’s complement representation
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1. n-bit Unsigned Integers

 Unsigned integers can represent zero and positive
integers, but not negative integers.
 The value of an unsigned integer is interpreted as "the
magnitude of its underlying binary pattern".
 Example:
 Suppose that n=8 and the binary pattern is
0100 0001B, the value of this unsigned integer is
1×20 + 1×26 = 65D.

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2. Signed Integers
A. Sign-and-Magnitude
 In daily usage, signed integers are represented by a plus or
minus sign and a value.
 In the computer, the uses of 0’s and 1’s take place.
 0 : plus ( positive)
 1 : minus (negative)
 The leftmost bit in a binary number is considered the sign
bit.
 The remaining (n-1) bits are used for magnitude.

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 Example-5
118

 Ex.1: Suppose that n=8 and the binary representation is 0 100

0001B.
Sign bit is 0 ⇒ positive
Absolute value is 100 0001B = 65D
Hence, the integer is +65D
 Ex.2: Suppose that n=8 and the binary representation is 1 000
0001B.
Sign bit is 1 ⇒ negative
Absolute value is 000 0001B = 1D
Hence, the integer is -1D
 Ex.3: Suppose that n=8 and the binary representation is 0 000
0000B.
Sign bit is 0 ⇒ positive
Absolute value is 000 0000B = 0D 12/10/2023
119

 The drawbacks of sign-magnitude representation are:

 There are two representations for the number zero (0000
0000B and 1000 0000B) , which could lead to inefficiency
and confusion.
 Positive and negative integers need to be processed
separately.

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B. 1's Complement Representation

 Again, the most significant bit (msb) is the sign bit, with
value of 0 representing positive integers and 1 representing
negative integers.
 The remaining n-1 bits represents the magnitude of the
integer, as follows:
 For positive integers, the absolute value of the integer is
equal to "the magnitude of the (n-1)-bit binary pattern".
 For negative integers, the absolute value of the integer is
equal to "the magnitude of the complement (inverse) of
the (n-1)-bit binary pattern" (hence called 1's
complement).
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 Example-6
122

 Ex.1: Suppose that n=8 and the binary representation is 0 100

0001B.
Sign bit is 0 ⇒ positive
Absolute value is 10000001B = 65D
Hence, the integer is +65D
 Ex.2: Suppose that n=8 and the binary representation is 1 000
0001B.
Sign bit is 1 ⇒ negative
Absolute value is the complement of 000 0001B = 111 1110B =
126 D
Hence, the integer is -126D
 Ex.3: Suppose that n=8 and the binary representation is 0 000
0000B.
Sign bit is 0 ⇒ positive
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Absolute value is 000 0000B = 0D
123

 The drawbacks of 1st complement :

 There are two representations (0000 0000B and 1111
1111B) for zero.
 The positive integers and negative integers need to be
processed separately.

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C. 2's Complement Representation

 Again, the most significant bit (msb) is the sign bit, with
value of 0 representing positive integers and 1 representing
negative integers.
 The remaining n-1 bits represents the magnitude of the
integer, as follows:
 For positive integers, the absolute value of the integer is
equal to "the magnitude of the (n-1)-bit binary pattern".
 For negative integers, the absolute value of the integer is
equal to "the magnitude of the complement of the (n-1)-
bit binary pattern plus one" (hence called 2's
complement).
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 Example-7
126

 Ex.1: Suppose that n=8 and the binary representation is 0 100

0001B.
Sign bit is 0 ⇒ positive
Absolute value is 100 0001B = 65D
Hence, the integer is +65D
 Ex.2: Suppose that n=8 and the binary representation is 1 000
0001B.
Sign bit is 1 ⇒ negative
Absolute value is the 2’s complement of 000 0001B = 111 1111B =
127 D
Hence, the integer is -127D
 Ex.3: Suppose that n=8 and the binary representation is 0 000
0000B.
Sign bit is 0 ⇒ positive
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Absolute value is 000 0000B = 0D
127 12/10/2023
128

Which signed
integer’s
representation that
the computer used?
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129

 Computers use 2's complement in representing

signed integers. This is because:
 There is only one representation for the number
zero in 2's complement, instead of two
representations in sign-magnitude and 1's complement.
 Positive and negative integers can be treated
together in addition and subtraction.
 Subtraction can be carried out using the "addition logic".

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 Exercise-9
130

 Show the actual binary operation

1. Addition of Two Positive Integers: Suppose
that n=8.
 65D + 5D = 70D
2. Subtraction is treated as Addition of a Positive
and a Negative Integers: Suppose that n=8.
 65D + (-5D) = 60D
3. Addition of Two Negative Integers: Suppose
that n=8.
 -65D - 5D = (-65D) + (-5D) = -70D

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 Floating point representation

 A floating-point number (or real number) can represent
 A very large (1.23×1088) or a very small (1.23×10-88) value.
 It could also represent very large negative number (-1.23×10 88)
and very small negative number (-1.23×10 -88), as well as zero.
 A floating-point number is typically expressed in the
scientific notation, with a fraction (F), and an
exponent (E) of a certain radix (r), in the form of
F×rE.
 Decimal numbers use radix of 10 (F×10E); while binary
numbers use radix of 2 (F×2E).
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 For example, the number 55.66 can be represented as

 5.566×101
 0.5566×102
 0.05566×103, and so on.
 We need NORMALIZATION ….
 The fractional part can be normalized
 In the normalized form, there is only a single non-zero digit
before the radix point.

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 It is important to note that floating-point numbers

suffer from loss of precision when represented with a
fixed number of bits (e.g., 32-bit or 64-bit).
 This is because there are infinite number of real numbers
(even within a small range of says 0.0 to 0.1). On the other
hand, a n-bit binary pattern can represent a finite 2n distinct
numbers.
 Hence, not all the real numbers can be represented.
The nearest approximation will be used instead,
resulted in loss of accuracy.

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 It is also important to note that floating number

arithmetic is very much less efficient than integer
arithmetic.
 It could be speed up with a so-called dedicated floating-
point co-processor.
 Hence, use integers if your application does not require
floating-point numbers.
 Thus a floating point number can be characterizing by
a triple of numbers: sign, exponent, and fraction.

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 Modern computers adopt IEEE 754 standard for

representing floating-point numbers. There are three
representation schemes:
1. 32-bit single-precision,
2. 64-bit double-precision and
3. 128-bit quad-precision.

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 Basic IEEE floating point number

Quadrupl
Single Double
e
No. of sign bit 1 1 1
No. of biased
exponent bit 8 11 15
No. of fraction 23 52 112
Total bit used 32 64 128
(28-1 -1) (211-1 -1) (215-1 -1)
Bias (2e-1 -1)
127 1023 16383
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 Exponent Biasing
 Usually signed integers are stored as two’s complement.
However, exponent in IEEE-754 floating point standard is
stored as offset binary.
 It also has many other names, like biased exponent or offset-k,
where k denotes an offset.

The exponent is biased by 2e-1 -1, where e is the number of bits
used for the exponent field (if e=8, then 28-1 -1= 128 -1=127).
 Biasing is done because exponents have to be signed values in
order to able to represent both tiny and huge values, but
two’s complement, the usual representation for signed values,
would make comparison harder.
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 To solve this, the exponent is biased before being

stored by adjusting its value to put it within an
unsigned range suitable for comparison.
 For example: to represent a number which has
exponent of 17 in exponent field 8 bits wide.
 Exponent field = 17 + 28-1 -1= 17+128-1=144

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 Single Precision
 The IEEE single precision floating point standard
representation requires a 32 bit word, which may be
represented as numbered from 0 to 31, left to right.
 The first bit is the sign bit, ‘S’, the next eight bits are
the exponent bits, ‘E’, and the final 23 bits are the
fraction ‘F’.

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The IEEE Floating Point Representation

Convert 153.7510 to the IEEE floating point format.
 Step 1 : convert into binary
 Step 2 : put into 1.xxxx X 2y format
 Step 3 : get the biased exponent (identify the exponent
first)
 Step 4 : get the sign (from the question)
 Step 5 : identify significand and mantissa
 Step 6 : put into the IEEE single precision format
 Step 7 : convert into hexadecimal
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 Exercise-10:
142

 Convert the number to the IEEE floating

point format
A. +3.5D
B. -0.75D
C. +1.25D

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 The IEEE Floating Point Representation

Convert C2F0 000016 in IEEE floating point format to the
decimal number.
 Step 1 : in hexadecimal
 Step 2 : convert into binary
 Step 3 : put into the IEEE single precision format
 Step 4 : get biased exponent (motive is to get the exponent y)
 Step 5 : get the sign
 Step 6 : identify significand and mantissa
 Step 7 :put into 1.xxxx X 2y
 Step 8 : identify actual number
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 Exercise-11:
145

 Determine the number

1. Suppose that IEEE-754 32-bit floating-point
representation pattern is 0 10000000 110 0000 0000
0000 0000 0000
2. Suppose that IEEE-754 32-bit floating-point
representation pattern is 1 01111110 100 0000 0000
0000 0000 0000.
3. Suppose that IEEE-754 32-bit floating-point
representation pattern is 1 01111110 000 0000 0000
0000 0000 0001.

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Questions?
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Thank You
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