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Lecture 5

This document discusses various diode circuit configurations including parallel, series-parallel, AND/OR gates, half-wave rectification, full-wave rectification using a bridge network and center-tapped transformer. It explains how diodes behave in each configuration and how to calculate voltage and current. Rectification circuits are analyzed using both ideal and practical diodes. The peak inverse voltage rating and its importance in rectifier design is also covered.

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ahmed mahmoud
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59 views29 pages

Lecture 5

This document discusses various diode circuit configurations including parallel, series-parallel, AND/OR gates, half-wave rectification, full-wave rectification using a bridge network and center-tapped transformer. It explains how diodes behave in each configuration and how to calculate voltage and current. Rectification circuits are analyzed using both ideal and practical diodes. The peak inverse voltage rating and its importance in rectifier design is also covered.

Uploaded by

ahmed mahmoud
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Diode

LECTURE 5 Applications
(cont.,)
INTRODUCTION
Once the basic behavior of a Diode device is understood, its
function and response in an infinite variety of configurations
can be examined.
This chapter will develop a working knowledge of the diode
in a variety of configurations using models appropriate for
the area of application.
By chapter’s end, the fundamental behavior pattern of diodes
in dc and ac networks should be clearly understood.
The analysis of electronic circuits can follow one of two
paths: using the actual characteristics or applying an
approximate model for the device.
PARALLEL AND SERIES–PARALLEL
CONFIGURATIONS
For the applied voltage the “pressure” of the source acts to establish a
current through each diode in the same direction as shown in Fig.
Since the resulting current direction matches that of the arrow in each
diode symbol and the applied voltage is greater than 0.7 V, both diodes are
in the “on” state.
The voltage across parallel elements is always the same and
EXAMPLE
Determine the voltage for the following network?

• One of the basic rules of network analysis: The voltage must be


the same across parallel elements.
EXAMPLE
Determine the currents , , and for the network?
AND/OR GATES
• That is, the 10-V level of Fig. is assigned a “1” for Boolean
algebra and the 0-V input is assigned a “0.”
• An OR gate is such that the output voltage level will be a 1 if
either or both inputs is a 1.
• The output is a 0 if both inputs are at the 0 level.
• AND gate is such that the output voltage level will be a 1
only if both inputs is a 1.
• The analysis of AND/OR gates is made easier by using the
approximate equivalent for a diode rather than the ideal
because we can stipulate that the voltage across the diode
must be 0.7 V positive for the silicon diode to switch to the
“on” state.
OR GATE
AND GATE
SINUSOIDAL The diode analysis will now be
INPUTS expanded to include time-varying
HALF-WAVE functions such as the sinusoidal
RECTIFICATI waveform and the square wave.
ON
WITH IDEAL DIODE.
𝑉 𝑑𝑐
To determine the average value of the rectified
signal, we can calculate the area under the curve
[ 0 to π] and divide the value by the period of
the rectified waveform.
= 1/2 π sin wt d wt
= / 2 π [-cos wt]from 0 to π
= /π
= 0.318
The process of removing one-half the input
signal to establish a dc level is called half wave
DC LEVEL rectification.
WITH PRACTICAL
DIODE
a. Sketch the output v o and determine the dc level of the
output for the network.
b. Repeat part (a) if the ideal diode is replaced by a
silicon diode.
c. Repeat parts (a) and (b) if V m is increased to 200 V?

EXAMP
LE
The peak inverse voltage (PIV) [or PRV (peak reverse
voltage)] rating of the diode is of primary importance in
the design of rectification systems.
Recall that it is the voltage rating that must not be
exceeded in the reverse-bias region or the diode will
enter the Zener avalanche region.

PIV
The dc level obtained from a sinusoidal input
can be improved 100% using a process called
full-wave rectification .
Since the area above the axis for one full cycle
is now twice that obtained for a half-wave
system, the dc level has also been doubled
FULL-
WAVE
RECTIFICA
TION
The most familiar network for
performing such a function appears in
the following Figure with its four diodes
in a bridge configuration.
BRIDG
E
NETW
ORK
1- DURING THE PERIOD T = 0
TO T / 2
2- DURING THE PERIOD
T = T/2 TO T
Bridge Network 𝐕𝐝𝐜
In case of ideal diode:
= 0.636
In case of real diode:
= 0.636 - 2 )
For the indicated loop the maximum voltage across R is V m
and the PIV rating is defined by :
PIV >=
CENTER-TAPPED
TRANSFORMER
A second popular full-wave rectifier appears in the
following figure with only two diodes but requiring a
center-tapped (CT) transformer to establish the input
signal across each section of the secondary of the
transformer.
CENTER-TAPPED OPERATION
During the positive portion of v i applied to the primary of the
transformer:

During the positive portion of vi applied to the primary of the


transformer, the network will appear as shown in Fig., with a
positive pulse across each section of the secondary coil.
D1 assumes the short-circuit equivalent and D2 the open-circuit
equivalent, as determined by the secondary voltages and the
resulting current directions.
During the negative portion of v i
applied to the primary of the
CONT., transformer:

During the negative portion of the input the network appears as


shown in Fig., reversing the roles of the diodes but maintaining
the same polarity for the voltage across the load resistor R.
PIV
The disadvantage of center-tapped is that each diode has to have PIV :
ASSIGNMENT
SOLUTION
A- For positive region:
Vom = Vim x 2 / (2+2) = ½ Vim
CONT.,
B- Negative region:
For the negative part of the input, the roles of the diodes
are interchanged and v o appears as shown in Fig.

The effect of removing two diodes from the bridge


configuration is therefore to reduce the available dc level
to the following: Vdc = 0.636(5 V) = 3.18 V
SHEET
Text Book Ch. 2

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