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VLSI - Design For Testability

DFT techniques add testability features to chip designs to make it easier to test for manufacturing defects. Tests are run at multiple manufacturing stages and may also be used after deployment to check proper functioning and diagnose any failures. The goal is to validate that no defects are present that could impact the product's correct operation.

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Mohammed Mian A
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77 views1 page

VLSI - Design For Testability

DFT techniques add testability features to chip designs to make it easier to test for manufacturing defects. Tests are run at multiple manufacturing stages and may also be used after deployment to check proper functioning and diagnose any failures. The goal is to validate that no defects are present that could impact the product's correct operation.

Uploaded by

Mohammed Mian A
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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VLSI _Design for Testability

Design for testing or design for testability (DFT) consists of IC design techniques that add testability features
to a hardware product design. The added features make it easier to develop and apply manufacturing tests to the
designed hardware. The purpose of manufacturing tests is to validate that the product hardware contains no
manufacturing defects that could adversely affect the product's correct functioning.
Tests are applied at several steps in the hardware manufacturing flow and, for certain products, may also be used
for hardware maintenance in the customer's environment. The tests are generally driven by test programs that
execute using automatic test equipment (ATE) or, in the case of system maintenance, inside the assembled system
itself. In addition to finding and indicating the presence of defects (i.e., the test fails), tests may be able to log
diagnostic information about the nature of the encountered test fails. The diagnostic information can be used to
locate the source of the failure.

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