ANALYSIS OF CLOCKED SEQUENTIAL CIRCUITS

 Analysis refers to describing what a given circuit will do under certain operating conditions.

 The behavior of clocked sequential circuits is determined from inputs, outputs and the states of flip-flops.

 Algebraically, the behavior of clocked sequential circuits is described by means of state equations.

 A state equations specifies the next state as a function of the present state and inputs.

Analysis Procedure

1. Obtain the equations for the inputs of flip flops.

2. Obtain the output equations

3. Compile the state table for all possible inputs and state values.

4. Draw the state diagram.

ANALYSIS EXAMPLE

 Is this a clocked sequential circuit? - YES

 Memory type - D

 State variables - Two - A and B

 Inputs - One – x

 Outputs - One - y
FLIP FLOP INPUT EQUATIONS

 Equations on D input of flip flops –

DA = Ax + Bx

DB = A’x

A and B are current states

A(t) = A, B(t) = B

DA and DB are next states

A(t + 1) = DA, B(t + 1) = DB

The values of A and B would be DA and DB at next clock edge

OUTPUT EQUATIONS AND STATE TABLE
 Output – y = (A + B)x’

 State Table shows the next state and output in tabular form.

 Next state equations – A(t + 1) = Ax + Bx , B(t + 1) = A’x

 Output equation - y = (A + B)x’

STATE DIAGRAM
 State diagram is a graphical representation of a state table.

 The circles represent the states.

 2 state variables – 4 possible states

COMBINATIONAL vs SEQUENTIAL ANALYSIS
Combinational Circuits

- Obtain the Boolean equations

- Form a truth table

Output is a function of input only

Sequential Circuits

- Obtain the next state equations

- Obtain the output equations

- Compile the state table

- Draw the state diagram

Output is a function of input as well as current state

EXAMPLE
EXAMPLE
FLIP FLOP CHARACTERISITC EQUATIONS - RECALL
SEQUENTIAL CIRCUIT WITH T FLIP FLOPS
SEQUENTIAL CIRCUIT WITH T FLIP FLOPS
SEQUENTIAL CIRCUIT WITH T FLIP FLOPS
SEQUENTIAL CIRCUIT WITH JK FLIP FLOPS
SEQUENTIAL CIRCUIT WITH JK FLIP FLOPS
MEALY AND MOORE SEQUENTIAL CIRCUITS
 There are two ways to design a clocked sequential circuit –

1. Mealy Machine – Outputs depends on present state and inputs

2. Moore Machine – Outputs depend on present state only

MEALY MACHINE
 The outputs are a function of the present state and the inputs.

 The outputs are not synchronized with the CLOCK.

 Outputs may change if inputs change during the CLOCK cycle.

 Outputs may have momentary false values (glitches).

 The final outputs are present just before the edge of the CLOCK.
TRACING A MEALY STATE DIAGRAM

 Initial state AB is unknown.

 Even though the initial state is unknown, input x = 0 forces a transition to state AB = 0, regardless of the
present state.

 Reset input could also be used to initialize the state to 00.

FALSE OUTPUT IN TIMING DIAGRAM
MOORE MACHINE
 The outputs are a function of the flip flop outputs only.

 The outputs depend on the present state only.

 The outputs are synchronized with the CLOCK.

 Outputs do not have any momentary false values (glitches).

 Some designs might have a mix of Mealy and Moore circuits.

TRACING A MOORE STATE DIAGRAM

 Initial state AB and output are unknown.

 Input x = 0, resets AB to 00.

 Reset input could also be used to initialize the state to 00.

TIMING DIAGRAM
SEQUENCE DETECTOR
SEQUENCE DETECTOR
SEQUENCE DETECTOR
STATE REDUCTION AND ASSIGNMENT
STATE REDUCTION AND ASSIGNMENT
STATE REDUCTION AND ASSIGNMENT
STATE REDUCTION AND ASSIGNMENT
DESIGN PROCEDURE
1. Specification – e.g. Verbal description

2. Formulation – Interpret the specification to obtain a state diagram and a state table

3. State Assignment - Assign binary codes to symbolic states

4. Flip-Flop Input Equation Determination - Select flip-flop types and derive flip-flop input
equations from next state entries in the state table

5. Output Equation Determination - Derive output equations from output entries in the state
table

6. Optimization - Optimize the combinational logic equations in 4, 5 above, e.g. using K-maps

7. Technology Mapping - Find circuit from equations and map to a given gate & flip-flop
technology

8. Verification - Verify correctness of final design

SPECIFICATION
Specification can be through:

 Written description

 Mathematical description

 Hardware description language

 Tabular description

 Logic equation description

 Diagram that describes operation

FORMULATION
 A state is an abstraction of the history of the past applied inputs to the circuit.

 Examples:

State A may represent the fact that three successive 1’s have occurred at the input.

State B may represent the fact that a 0 followed by a 1 have occurred as the most recent past two inputs.

0001100011011100

Machine enters State A here

Machine enters State B here

 Machine can only be in one state at any given time

STATE INITIALIZATION
 When a sequential circuit is turned on, the state of the flip flops is unknown (Q could be 1 or 0).

 Before meaningful operation, we usually bring the circuit to an initial known state, e.g. by resetting
all flip flops to 0’s.

 This is often done asynchronously through dedicated direct S/R inputs to the FFs.

 It can also be done synchronously by going through the clocked FF inputs

EXAMPLE: BIT SEQUENCE RECOGNIZER: 1101

1. Verbal Specifications:

X Z
Input 1101
Output
Recognizer

Detect the occurrence of bit sequence 1101 whenever it occurs on input X and indicate this detection
by raising an output Z high
i.e. normally output Z = 0 until sequence 1101 occurs
i.e. until input X = 1 and
110 was the last sub-sequence received i.e. system was in the state ‘110’

Is this a Mealy or a Moore model?

EXAMPLE: BIT SEQUENCE RECOGNIZER: 1101
2. Formulation:

 Begin in an initial state in which NONE of the initial portion of the sequence has occurred (typically “reset”
state).

 Add a state which recognizes that the first symbol in the target sequence (1) has occurred.

 Add states that recognize each successive symbol occurring.

 Add state transition arcs which specify what happens when a symbol not contributing to the target sequence
has occurred.
Has sub-sequences: 1, 11, 110

 The 1/1 arc from D means full sequence is detected & Z = 1. But why does it go to B? Since this ‘1’ could be the
first 1 in a new sequence and thus needs to be remembered as ‘1’!
EXAMPLE: BIT SEQUENCE RECOGNIZER: 1101
 At each state, the input X could have any of two values, so 2 arcs must emanate from each state (X = 0 and X =
1).

 Each state must have 2 arcs exiting.

EXAMPLE: BIT SEQUENCE RECOGNIZER: 1101
STATE TABLE

 From the State Diagram, we can fill in the 2-D State Table.

 There are 4 states, one input, and one output.

 Two dimensional table with four rows, one for each current state.

PRESENT STATE NEXT STATE OUTPUT

X=0 X=1 X=0 X=1

A A B 0 0

B A C 0 0

C D C 0 0

D A B 0 1

 Output depends on input - Mealy

EXAMPLE: BIT SEQUENCE RECOGNIZER: 1101
STATE ASSIGNMENT

 4 states (A, B, C, D)

 2 FFs, No unused states.

 Let A = 00 (to suit being a Reset state), B = 01, C = 11, D = 10.

EXAMPLE: BIT SEQUENCE RECOGNIZER: 1101
FLIP – FLOP INPUT EQUATION AND OUTPUT EQUATION

Consider use of D Flip-Flops

EXAMPLE: BIT SEQUENCE RECOGNIZER: 1101
FLIP – FLOP INPUT EQUATION AND OUTPUT EQUATION
EXAMPLE: BIT SEQUENCE RECOGNIZER: 1101

SEQUENTIAL CIRCUIT

Asynchronous Reset
To Initial State A (AB = 00)
EXAMPLE
EXAMPLE
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EXAMPLE
EXAMPLE – MOORE ELEVATOR
 Design an elevator which moves between ground floor and first floor. The output is one when it is at
state 1 and zero when it is at zero state.
EXAMPLE – MOORE ELEVATOR
EXAMPLE
 Design the machine with following state diagram.
EXAMPLE
EXAMPLE
EXAMPLE
EXAMPLE
 Design an old vending machine.

Assumptions –

1. Only one item is available in the vending machine.

2. Opens the slot when Rs 15 are entered.

3. No change is returned.

4. Single slot for entering coins as well as notes.

5. Only one unit of currency can be entered at a time.

EXAMPLE
Possible inputs –

 5, 5, 5

 10, 5

 5, 10

 10, 10

 5, 5, 10

Input N – Rs 5

Input D - Rs 10
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