Data Communication CSE 315

- Line Coding -
Prof. Dr. A.K.M. Muzahidul Islam
Computer Science & Engineering (CSE)
United International University (UIU)

Fall 2021
 I’ll paint it on the walls
‘Cause I’m the one at faults
I’ll never fight again
And, this is how it ends!

2
Resources

■ B. A. Forouzen Chapter 4
 Outline

• Digital Transmission Overview

• Line Coding Schemes

• Some Other Schemes

 Digital Transmission

■ Computer Networks are designed to send

information from one point to another
■ Digital Data -> Digital Signal
■ Line Coding
■ Block Coding
■ Scrambling
■ Analog Data -> Digital Signal
■ PCM (Pulse Code Modulation)
■ DM (Delta Modulation)

4.5
 Line Coding

■ A process of converting digital data to digital

signals.
■ E.g., Text, Numbers, Graphical Images, audio or
video
■ Converting a string of 1’s and 0’s (digital
data) into a sequence of signals that denote
the 1’s and 0’s.
■ For example, a high voltage level (+V) could
represent a “1” and a low voltage level (0 or -V)
could represent a “0”.

4.6
 Line Coding

Converting sequence of bits into digital signal.

Example: 01011101 -> Line Coding ->

0- Low Signal

1 – High Signal

7 Figure 4.1 Line coding

 Figure 4.2 Line coding and decoding

4.8
 Properties of Line Coding

• Bandwidth use is reduced

• The power is efficiently used
• Probability of error is reduced
• Error detection and correction capabilities
• Cross talk between channels is minimized

9
 Line encoding

■ To correctly interpret the signals received

from the sender, the receiver’s bit intervals
must correspond exactly to the sender’s bit
intervals.
■ Self synchronization - the clocks at the sender
and the receiver must have the same bit
interval.
■ If the receiver clock is faster or slower it will
misinterpret the incoming bit stream.

4.10
 Figure 4.3 Effect of lack of
synchronization

The receiver has a shorter bit duration.

The sender sends 10110001
The receiver receives 110111000011.
4.11
 Example
In a digital transmission, the receiver clock is 0.1 percent
faster than the sender clock. How many extra bits per
second does the receiver receives if the data rate is 1 kbps?
How many if the data rate is 1 Mbps?
Solutions:
■ At 1 kbps, the receiver receives 1001 bps instead of 1000
bps.
■ 1000 bits sent 1001 bit received 1 extra bps
■ At 1 Mbps, the receiver receives 1,001,000 bps instead of
1,000,000 bps.
■ 1,000,000 bits sent 1,001,000 bits received
1000 extra bps
4.12
 ■ Given, receiver clock is 0.1% faster than sender clock.
■ At 1 Mbps bits send by sender = 1000000 receiver clock
is 0.1% faster than sender clock
■ So Extra bits received by receiver =
1000000 * (0.1/100) =1000 bits
■ Total bits received by received = 1001000 bits Extra bit
per second received by receiver = 1000 bps.

4.13
 Figure 4.4 Line coding schemes

4.14
 Classification of Line Coding

▪ Unipolar
▪ Uses only one voltage level other than 0
▪ e.g. RZ and NRZ
▪ Polar
▪ Uses two voltage level other than 0
▪ RZ, NRZ, Manchester
▪ Bipolar
▪ Uses three voltage levels positive, negative, and
zero
▪ E.g., AMI

15
 Unipolar

■ All signal levels are on one side of the

time axis - either above or below
■ It has no synchronization
■ No error detection
■ costly in power consumption.

Advantage:
■ Simple

4.16
 Figure 4.5.1 Unipolar NRZ scheme

Exercise : 10011100
00101110
NRZ (Non-Return-to-Zero) – Signal does not
return to zero at the middle of the bit.
•Positive Voltage defines bit 1
•Zero voltage defines bit 0.
4.17
Figure 4.5.2 Unipolar RZ scheme

In this type of unipolar signaling,

Half of the bit duration remains high but

it immediately returns to zero and shows

the absence of pulse during the

remaining half of the bit duration.

Advantages
•Exercise : 10011100
It is simple.
00101110
• The spectral line present at the symbol rate can be used as a
clock.
Disadvantages
• No error correction.
 Polar - NRZ

■ The voltages are on both sides of the

time axis. (+V and -V)
■ Polar NRZ scheme can be implemented with
two voltages. e.g. +V for 1 and -V for 0.
■ There are two versions:
■ NRZ - Level (NRZ-L) - positive voltage for one
symbol and negative for the other
■ NRZ - Inversion (NRZ-I) - the change or lack of
change in polarity determines the value of a
symbol. e.g. a “1” symbol inverts the polarity a “0”
does not.

4.19
 Figure 4.6 Polar NRZ-L and NRZ-I schemes

0-Hero Exercise: (i) 100110101

1-Zeo (ii) 110101011

0-No Transition Exercise: (i) 100111100

1-Transition (ii) 001011100

4.20
 Note

In NRZ-L the level of the voltage

determines the value of the bit.
In NRZ-I the inversion
or the lack of inversion
determines the value of the bit.

4.21
 Note

NRZ-L and NRZ-I both have no self

synchronization &no error detection.
Both are relatively simple to implement.

4.22
 Polar - RZ
■ The Return to Zero (RZ) scheme uses three
voltage values. +V, 0V, -V.
■ Each symbol has a transition in the middle.
Either from high to zero - Z or from low to
zero – reverse Z.
■ This scheme has more signal transitions (two
per bit) and therefore requires a wider
bandwidth.
■ Self synchronization - transition indicates
symbol value.(Advantage)
■ More complex as it uses three voltage level. It
has no error detection capability.
(Disadvantage.)
4.23
 Figure 4.7 Polar RZ scheme

1- “z” shape in the above

0- reverse “z” shape below

Exercise: 110011000
110001011

4.24
 Polar - Biphase: Manchester and
Differential Manchester
■ Manchester coding consists of combining the
NRZ-L and RZ schemes.
■ Every symbol has a level transition in the middle:
from high to low or low to high.
■ Uses only two voltage levels.
■ Differential Manchester coding consists of
combining the NRZ-I and RZ schemes.
■ Every symbol has a level transition in the middle.
But the level at the beginning of the symbol
is determined by the symbol value. One
symbol causes a level change the other does
not.
4.25
 Figure 4.8 Polar biphase: Manchester and differential Manchester
schemes
Exercise: (i) 10011010
(ii) 10011100

0- Transition
1-No Transition
First time always negative to Exercise: (i) 11010101
(ii) 01101101
4.26 positive transition.
 Note

In Manchester and differential

Manchester encoding, the transition
at the middle of the bit is used for
synchronization.

4.27
 Bipolar - AMI and Pseudoternary
■ Code uses 3 voltage levels: - +V, 0, -V, to
represent the symbols (note not transitions
to zero as in RZ).
■ Voltage level for one symbol is at “0” and the
other alternates between + & -.
■ Bipolar Alternate Mark Inversion (AMI) - the
“0” symbol is represented by zero voltage and
the “1” symbol alternates between +V and -V.
■ Pseudoternary is the reverse of AMI.

4.28
 Figure 4.9 Bipolar schemes: AMI and pseudoternary
0- Draw line on the reference line
1- Draw line above/below (alter) of the reference line
Exercise: (i) 10011100
(ii) 00101110

1- Draw line on the reference line

0- Draw line above/below (alter) of the reference line
Exercise: (i) 10011100
(ii) 00101110
4.29
 Figure 4.9 Bipolar schemes: AMI and pseudoternary

■ Advantage:
■ Inbuilt error detection technique.

4.30