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26a Lab6 Intro

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18 views5 pages

26a Lab6 Intro

xilinx tutorial slides

Uploaded by

karthikp207
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Lab6 Intro

Creating a Processor System

Zynq
Vivado HLS 2015.2 Version

This material exempt per Department of Commerce license exception TSU © Copyright 2015 Xilinx
Objectives

After completing this lab, you will be able to:


– Profile an application
– Understand the steps and directives involved in creating a IP-XACT adapter from a synthesized
design in Vivado HLS
– Create a processor system using IP Integrator in Vivado
– Integrate the generated IP-XACT adapter into the created processor system

Lab6 Intro 26a- 2 © Copyright 2015 Xilinx


The Design

The design consists of a FIR filter to filter a 4 KHz tone added to a CD quality (48 KHz)
music. This lab requires you to develop a peripheral core of the designed filter that can
be instantiated in a processor system. The processor system will acquire a stereo
music using on-board CODEC chip and I2S controller, process (bandstop filter) it
through the designed filter, and output back to the speaker.
The FIR filter, developed in software, is first profiled, then is pass through the Vivado
HLS design flow to export it as a hardware accelerator which in turn is used in
embedded system.

Lab6 Intro 26a- 3 © Copyright 2015 Xilinx


Procedure

Create a Vivado project to build an embedded system with FIR filter running in software
Profile the software routine
Create a Vivado HLS project for the FIR filter
Run simulation and verify functionality
Synthesize the design
Run RTL/C Co-simulation
Setup IP-XACT adapter and generate the IP-XACT adapter
Update the Vivado project with the adapter
Profile the application with the FIR in hardware
Run the application in hardware

Lab6 Intro 26a- 4 © Copyright 2015 Xilinx


Summary

In this lab, you profiled the FIR software routine. Then you synthesized the routine in
Vivado HLS. Next, you used an INTERFACE directive to create an IP-XACT adapter. You
generated the IP-XACT adapter. You then updated the processor system using IP
Integrator, integrated the generated IP core, and tested the system with the provided
application

Lab6 Intro 26a- 5 © Copyright 2015 Xilinx

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