Chapter 4

MARIE:
An Introduction to a Simple Computer

Prepared by Dr. Ahmad Mikati

 Lecture Overview
Introduction to this Lecture's activities
In this lecture, you will learn how computer components work, and how they fit
together to create useful computer systems. This lecture illustrates basic
computer organization and introduces many fundamental concepts, including the
fetch-decode-execute cycle, the data path, clocks and buses, register transfer
notation, and of course, the CPU.

In addition, you will learn how the Instruction Set Architecture (ISA) plays the role
of an interface between the software and Hardware. Mainly, you will have a look
at MARIE, which has a very simple, yet powerful, instruction set.

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 Lecture Overview
After completing the lecture, you will be able to:
 Identify the components common to every modern computer
system.
 Explain how each component contributes to program execution.
 Develop a simple architecture to illuminate the basic concepts that
relate to some real architectures.
 Describe how the program assembly process works.

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 Lecture Overview

 Introduction
• CPU Basics and Organization
• The Bus
• Clocks
• The Input/Output Subsystem
• Memory Organization and Addressing
• Interrupts
 Marie
 Instruction processing
 A simple program
 Extending our ISA
November 27, 2023 TM103 - Arab Open University 4
 Introduction

From Chapter 1, 2 and 3 we learned about:

• Computer systems and components
• How data is stored and manipulated inside different
computer systems.
• The fundamental components of digital circuits.
From now on, we will be interested in:
• How computer components work?
• and how they fit together to create useful computer
systems?

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 The Von Neumann model

 The Von Neumann architecture is shown in Figure 1.4

 It satisfies at least the following characteristics
• Consists of three hardware systems
- A central processing unit (CPU) with a control unit, an arithmetic
logic unit (ALU), registers (small storage areas), and a program
counter;
- a main-memory system, which holds programs that control the
computer’s operation;
- and an I/O system.
• Capacity to carry out sequential instruction processing
• Contains a single path, between the main memory system
and the control unit of the CPU

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 The Von Neumann model

• A Memory stores
both data and
program instructions
(both binary!)
• The CPU fetches,
decodes, and
executes program
instructions
sequentially

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 The Von Neumann model

 Program instructions are stored inside the main memory

 The machine runs the programs sequentially (instruction per
instruction – machine instruction)
 Each machine instruction is fetched, decoded and executed during
one cycle known as the von Neumann execution cycle (also called the
fetch-decode-execute cycle)
 One iteration of the cycle is as follows:
1. The control unit fetches the next program instruction from the memory,
using the program counter to determine where the instruction is located.
2. The instruction is decoded into a language the ALU can understand.
3. Any data operands required to execute the instruction are fetched from
memory and placed into registers within the CPU.
4. The ALU executes the instruction and places the results in registers or
memory.

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 The Von Neumann model
1. Fetch
Instruction 1
• PC indicates
Instruction 2
the iteration Instruction 3
Instruction 3
number Data 1 Data 2 Instruction 4
• CU fill the
instruction
register …
…
2. Decode …
• what ALU Instruction N
should do
(add, multiply,
…)?
• Fill registers
with needed
data
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 The Von Neumann model

3. Execute Instruction 1
• Execute the Instruction 2
Instruction 3
instruction Instruction 3

• Place the Data 1 Data 2 Instruction 4

results in Result

registers or
…
memory …
…
Instruction N

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 CPU Basics and Organization

What is inside the Box?

The central processing unit (CPU) is responsible for fetching program

instructions, decoding each instruction that is fetched, and performing the
indicated sequence on the correct data.

The computer’s CPU or Processor

– Fetches the program instructions,
– Decodes each instruction that is fetched , and
– Executes the indicated sequence of operations on the data

To introduce the simple architecture in the next section, we first examine, in

general, the microarchitecture that exists at the control level of modern
computers.

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 CPU Basics and Organization

The two principal parts of the CPU are the Datapath and the
Control unit.
– Datapath - consists of an arithmetic-logic unit (ALU) and network of
storage units (registers) that are interconnected by a data bus that is
also connected to main memory.
– Control Unit - responsible for sequencing the operations and making
sure the correct data is in the correct place at the correct time.

Registers hold data that can be readily accessed by the CPU. They are places
to store a wide variety of data (Numerical data, Addresses, Control
information,..). They are located on the processor so information can be
accessed very quickly
– The control unit directly accesses data inside the registers

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 CPU Basics and Organization
“General Purpose registers” are registers available to the programmer.
“Special Purpose registers” always stores the same type of data
Examples: Index registers, status registers, etc.

Registers can be implemented using D flip-flops (recall that A D flip-flop

could be used as a storage element).
For example, a 32-bit register requires 32 D flip-flops.
- The size of the registers fixes the “word size”

The arithmetic-logic unit (ALU) carries out logical and arithmetic

operations as directed by the control unit.

The control unit (CU) determines which actions to carry out according to
the values in a program counter register and a status register.
• It fetches and decodes sequentially the instructions stocked in the
main memory.
• It27,also
November 2023 monitors the execution of these
TM103 - Arab Open Universityinstructions and the transfer
13
of all information.
 Computer Buses and Clocks

The CPU communicates with the other components via a Bus. Moreover, and
in order to maintain synchronization of the activities, the computer contains
at least one clock.

Buses:
A Bus is a set of wires that simultaneously convey a single bit along each line
(parallel movement). It connects multiple subsystems within the system.

A Bus could be “Point-to-Point” or “Multipoint” (also referred to as

“Common Pathway”)

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 Computer Buses and Clocks

 A point-to-point bus connects

two specific components

Figure 4.1: Point-to-point bus

 A multipoint bus is shared by several devices

• Bus protocols are used to manage the bus access by these
devices

Multipoint Bus

Figure 4.2: Multipoint bus

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 Computer Buses and Clocks
A typical bus consists of three main components
• Data lines: are dedicated to moving data (the actual information that
must be moved).
• Control lines: indicate which device has permission to use the bus
and for what purpose (reading or writing from memory or from an
I/O device, …)
• Address lines: indicate the location (in memory, for example) that the
data should be either read from or written to.
Power lines are also required to provide the electrical power necessary

Figure 4.3: Components of a typical Bus

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 Computer Buses and Clocks

Clocks:
Every computer contains at least one clock that synchronizes the activities
of its components.
The CPU requires a fixed number of clock ticks to execute each
instruction.
Moreover, instruction performance is often measured in clock cycles
instead of seconds.
The clock frequency, measured in megahertz or gigahertz, determines the
speed with which all operations are carried out.

Clock cycle time is the reciprocal of clock frequency: T= 1/F

Example 1: An 800 MHz clock has a cycle time of 1/(800x 106) seconds =
1.25 ns.
Example 2: If a machine has a 2ns cycle time, then it is a 500MHz machine.

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 Memory Addressing and Organization

 Computer memory consists of a linear array of addressable

storage cells that are similar to registers. It can be seen as a
matrix of bits, with each row having a length typically
equivalent to the word size of the machine (figure 4.4).

Figure 4.4: M 8-bit and N 16-bit Memory locations

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 Memory Addressing and Organization
Memory Addressing

Memory can be byte-addressable, or word-addressable, where a word

typically consists of two or more bytes.

Byte addressable: Each byte has its own address (each memory row
contains 8 bits only)

Word addressable: Each word has a unique address (each memory row
contains one word that can be larger than 8 bits).

Now, how many addresses, and how many address bits do we have in a
given memory?

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 Memory Addressing and Organization

To answer this question, you should be aware of:

 The type of addressing, whether word addressable or byte
addressable.
 The word size. For example, 8, 16, 32, 64 bits.
 The storage capacity of the memory. Memory is often referred to
using the notation L x W (length x Width). For example, 4M x 16
means the memory is 4M long (number of words) and it is 16 bits
wide (word size)

Example 1: How is a 4M x 16 word addressable memory organized?

• The word size is 16 bits.

• 4M means that we have 4 x 220 = 22 x 220 = 222 different words.
• These 222 words are numbered from 0 to 222 -1; each number represents the
address of only one word.
• So, each address is represented with at least 22 bits

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 Memory Addressing and Organization

Example 2: How many bits would you need to address a 2M × 32 memory if:
a) The memory is byte-addressable?
b) The memory is word-addressable?

Solution:
a) There are 2M × 4 bytes (recall that 32 bits =4 bytes), which equals
21 * 220* 22 bytes = 223 bytes. Hence, 23 bits are needed for an
address.

b) There are 2M words (32 bits are considered as 1 word, since the
memory is word addressable), which equals 21 × 220 words = 221
words. Hence, 21 bits are required for an address.

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 Memory Addressing and Organization
Memory Organization
Usually, computers’ physical Memory (RAM) is not made from a single high
capacity chip, but a group of lower capacities chips.

Access is more efficient when memory is organized into banks of chips with
the addresses interleaved across the chips.

The best way to explain how memory is organized, is found in the following
example.

Example: How to build a 32Kx16 word addressable RAM memory with only
2Kx8 RAM chips.

A 32Kx16 word addressable RAM memory can be created with 32 different

2Kx8 RAM chips. You could connect 16 rows and 2 columns of chips
together as shown in figure 4.5.

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 Memory Addressing and Organization

Figure 4.5: Building 32kx16 module from 2kx8 chips

The word size is now: 8x2=16 bits

The number of addresses (rows) is now: 2Kx16= 32K.
Therefore, what we have now is a memory module that has the size of
32Kx16.

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 Lecture Overview

 Introduction
 MARIE
• Introduction
• The Architecture
• Registers and Buses
• The Instruction Set Architecture
• Register Transfer Notation
 Instruction processing
 A simple program
 Extending our ISA
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 MARIE – Introduction
We are now familiar with computer components but how these are
connected together? How these work together?
Leonardo Da Vinci once said:
“When you wish to produce a result by means of an instrument, do not allow yourself
to complicate it”
In this part we will use a MARIE, A Machine Architecture that is Really
Intuitive and Easy.

A very simple architecture, MARIE, and its ISA are presented to allow you to
gain a full understanding of the basic architectural organization involved in
program execution.

MARIE exhibits the classical von Neumann design and includes a program
counter, an accumulator, an instruction register, 4096 bytes of memory, and
two addressing modes. Assembly language programming is introduced to
reinforce the concepts of instruction format, instruction mode, data format,
and control that are presented earlier.
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 MARIE – Architecture, Registers, and Buses

Architecture
The MARIE architecture is shown in the figure below:

Figure 4.6: MARIE architecture

The MARIE architecture has the following characteristics:

• Binary, two's complement data representation.
• Stored program, fixed word length data and instructions.
• 4K x 16 word-addressable main memory.
• 16-bit instructions: 4 bits for the opcode, 12 bits for the address.
• A 16-bit arithmetic logic unit (ALU).
• Seven registers for control and data movement.
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 MARIE – Architecture, Registers, and Buses

Registers

As you already know, registers are storage locations within

the CPU (as illustrated in the figure above).

The ALU portion of the CPU performs all the processing

(arithmetic operations, logic decisions, etc.).

The MARIE’s seven registers are used for very specific

purposes when programs are executing.

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 MARIE – Architecture, Registers, and Buses

 MARIE’s seven registers are:

• AC: Accumulator, a 16-bit register that holds a
conditional operator (e.g., "less than") or one
operand of a two-operand instruction.
• MAR: Memory address register, a 12-bit register
that holds the memory address of an instruction
or an operand of an instruction.
• MBR: Memory buffer register, a 16-bit register
that holds the data after its retrieval from, or
before its placement in memory.

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 MARIE – Architecture, Registers, and Buses

 MARIE’s seven registers ( continued):

• PC: Program counter, a 12-bit register that holds
the address of the next program instruction to be
executed.
• IR: Instruction register, a 16-bit register that holds
an instruction immediately preceding its
execution.
• InREG: Input register, an 8-bit register that holds
data read from an input device.
• OutREG: Output register, an 8-bit register that
holds data that is ready for the output device.

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 MARIE – Architecture, Registers, and Buses

Buses
MARIE cannot transfer data or instructions into or out of registers
without a bus.
In MARIE, we assume a common bus scheme
The registers are interconnected. They are also connected with main
memory through a common data bus.
A unique number that is set on the control lines whenever that device is
required to carry out an operation identifies each device on the bus.

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 MARIE – Architecture, Registers, and Buses

Separate connections are also provided between the accumulator

and the memory buffer register, between the ALU and the
accumulator and memory buffer register. This permits data
transfer between these devices without use of the main data bus.

 The Data path in MARIE is shown in

figure 4.7.
• Note that a data word (that is
an instruction) in the main
memory travels a relatively long
path before achieving the IR!

Figure 4.7: Data path in MARIE

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 The Instruction Set Architecture (ISA)

MARIE has a very simple, yet powerful, instruction set.

The Instruction Set Architecture (ISA) specifies the format of its
instructions and the primitive operations that the machine can perform.
The ISA is an interface between a computer’s hardware and its software.
Some ISAs include hundreds of different instructions for processing data
and controlling program execution.
For MARIE, each instruction consists of 16 bits
These bits are organized as follows:
• Opcode: 4 bits (bits 12 to 15), specifies the instruction to be
executed (which allows for a total of 24=16 instructions, but only 13
are used)
• Address: 12-bits (bits 0 to 11), forms an address.

Figure 4.8: Format of the MARIE instruction

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 The Instruction Set Architecture (ISA)

The fundamental MARIE instructions are:

Table 4.1: Fundamental MARIE instructions

Memorize
this table!

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 The Instruction Set Architecture (ISA)- Example

AC x y z Input Output
Initial Value 5 10 2 0
Load x 10 10 2 0
Store y 10 10 10 0
Add x 20 10 10 0
Subt y 10 10 10 0
Input 3 10 10 0 3
Skipcond 800 3 10 10 0
Jump finish 3 10 10 0
Store z 3 10 10 3
Add y 13 10 10 3
finish, Output 13 10 10 3 13
Halt
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 The Instruction Set Architecture (ISA)

To understand how things work, let us examine the instruction format

used in MARIE.
Suppose that we have the following 16-bit instruction:

Figure 4.9: Load 007 instruction format

The leftmost 4 bits indicate the opcode or the instruction to be executed.

0001 is binary for 1, which represents the Load instruction. The remaining 12
bits indicate the address of the value we are loading, which is the address 7 in
main memory.
This instructions causes the data found in address 7 in main memory to be
copied to the accumulator, AC.
Note that the value of address 7 in main memory remains there, as we have
only taken a copy of it.
However, any previous data found in the AC will be overwritten when we use
the Load instruction.
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 The Instruction Set Architecture (ISA)

Let us have another example:

Suppose that we have the following 16-bit instruction:

Figure 4.10: ADD 00E instruction format

The leftmost four bits, 0011, are equal to 3, which is the Add instruction.
The address bits indicate address 00E in hex (or 14 in decimal). This
means that the order will be given to go to main memory, get the data
value at address 00E, and add this value to the AC.
The new value in the AC would then be the sum of the old value of the
AC and the data fetched from address 00E.

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 The Instruction Set Architecture (ISA)

One important instruction is “Skipcond”

When the Skipcond instruction is executed, the value stored in the AC
must be inspected:
- The next instruction is skipped, if the condition tested is True.
- The next instruction is not skipped, if the condition tested is False.

Bits 11 and 10 (say b11b10) in the address field specify the condition to
be tested:
- b11b10 = 00: The CPU tests if AC < 0
- b11b10 = 01: The CPU tests if AC = 0
- b11b10 = 10: The CPU tests if AC > 0

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 The Instruction Set Architecture (ISA)

Example: Figure 4.11 is a bit pattern for a SKIPCOND instruction, as it

would appear in the IR:

Figure 4.11: Skipcond 400 instruction format

In figure 4.11, we see that the opcode is 8 and b11b10 (bits 11 and 10)are 01,
meaning that the next instruction will be skipped if the value in the AC is
equal to zero.
In general, we use:
- SKIPCOND 000 which means skip the next instruction if the AC <0.
- SKIPCOND 400 which means skip the next instruction if the AC =0.
- SKIPCOND 800 which means skip the next instruction if the AC >0.

Note that 000, 400 and 800 are in base 16. They are equivalent to 12 bits
(Address part).
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 Register Transfer Notation

MARIE instruction appears to be very simplistic.

Actually, at the component level, each instruction involves multiple
operations called “micro-operations”
Register Transfer Language (RTL), or Register Transfer Notation (RTN)
specifies the exact sequence of micro-operations that are carried out by
an instruction.

In the MARIE RTL, we will use the following notations:

- M[X]: to indicate the actual data value stored in memory location X
- ←: to indicate the transfer of bytes to a register or memory location
We will present the RTL for each of the instructions in the ISA for MARIE.

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 Register Transfer Notation

 Load X (loads the contents of memory location X into the AC)

MAR← X Place the address X in MAR;

MBR← M[MAR] The data M[MAR] at location address MAR

is moved into the MBR;
AC← MBR The content of MBR is placed in the AC.

 Store X (stores the contents of AC into the memory location X)

MAR← X Place the address X in MAR;
MBR← AC Place the content of AC in MBR
M[MAR]← MBR Place the content of MBR in the memory
location MAR (M[MAR] is replaced by MBR)

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 Register Transfer Notation

 Add X (The data value stored at address X is added to the AC).

MAR← X Place the address X in MAR;

MBR← M[MAR] Place the data M[MAR] at location address

MAR in MBR;
AC← AC + MBR Place the sum AC + MBR in AC

 Subt X (The data value stored at address X is subtracted from AC).

MAR← X Place the address X in MAR;

MBR← M[MAR] Place the data M[MAR] at location address

MAR in MBR;
AC← AC - MBR Place AC - MBR in AC

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 Register Transfer Notation

 Input (Inputs a value from the keyboard into AC)

AC← InREG Place the content of InREG (contains the input) in the
AC.

 Output (Outputs the value in AC to the display)

OutREG← AC Place the content of AC (contains the output) in the
OutREG (to send data to the display)

 Halt (Terminates the program)

no need for any RTL!

 Jump X (unconditional branch to the given address, X)

PC← X Load X into the PC

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 Register Transfer Notation

 Skipcond
if IR[11–10] = 00 then {if bits 10 and 11 in the IR are
both 0}

if AC < 0 then PC ← PC+1

else if IR[11–10] = 01 then {if bit 11 = 0 and bit 10 = 1}
if AC = 0 then PC ← PC + 1
else if IR[11–10] = 10 then {if bit 11 = 1 and bit 10 = 0}
if AC > 0 then PC ← PC + 1

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 Register Transfer Notation

Machine Cycle
It is worth mentioning that MARIE, like any other computer architecture, follows the
basic machine cycle: the fetch, decode, and execute cycle.

• The fetch-decode-execute cycle is the series

of steps that a computer carries out when
it runs a program.
• We first have to fetch an instruction from
memory, and place it into the IR.
• Once in the IR, it is decoded to determine
what needs to be done next.
• If a memory value (operand) is involved in
the operation, it is retrieved and placed
into the MBR.
• With everything in place, the instruction is
executed.
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 Lecture Overview

 Introduction
 MARIE
 Instruction processing
 A simple program
 Extending our ISA

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 A simple program

The table below shows a program written in assembly language for MARIE
What does this program do?

Table 4.2: A program To Add Two Numbers

This program simply adds to numbers and stores the result in the main memory.
- It loads the value stored at the location address 10416 into AC (the value is
002316 = 3510)
- It adds this value to the value stored at the location address 105 16 (the value is
FFE916 = (-23)10)
- Stores the sum into the location address 10616.
So, what 27,
November will be stored in the location
2023 address
TM103 - Arab 10616?
Open University 46
 A simple program

This program simply adds to numbers and stores the result in

the main memory.
• It loads the value stored at the location address 10416 into AC (the
value is 002316 = 3510)
• It adds this value to the value stored at the location address 10516
(the value is FFE916 = (-23)10)
• Stores the sum into the location address 10616.
- So what will be stored in the location address 10616?
 Now let us discover what happens during each “Fetch,
decode, execute” cycle.

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 A simple program

Now, let us discover what happens during each “Fetch, decode, execute” cycle.
The tables below show the effect of each instruction on the registers:

• Load 104:

Table 4.3: Fetch-decode-execute cycle of Load 104

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 A simple program

• Add 105:

Table 4.4: Fetch-decode-execute cycle of Add 105

• Store 106:

Table 4.5: Fetch-decode-execute cycle of Store 106

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TM103 - Arab Open University
 A simple program
Directives and Labels
An assembler directive is an instruction that is not supposed to be
translated into machine code.
There are four directives that the MARIE assembler recognizes:

The first of these is the origination directive, ORG. The ORG directive controls the
starting address of your program. If you do not include an ORG directive in your
code, the first address of your program is automatically 000h.

The other three directives enable you to put constants in your program as decimal
(DEC), octal (OCT), and hexadecimal (HEX) numbers.

In assembly language, we can also use labels in order to clarify the

program.
Substituting simple alphanumeric names for the opcodes makes
programming much easier. We can also substitute labels (simple names)
to identify or name particular memory addresses, making the task of
writing assembly programs even simpler.
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 A simple program
For example, in our program to add two numbers, we can use labels to
indicate the memory addresses, thus making it unnecessary to know the
exact memory address of the operands for instructions.

Table 4.6 shows how labels and directives could be used:

Table 4.6: Using Labels and Directives in MARIE

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 Lecture Overview

 Introduction
 MARIE
 Instruction processing
 A simple program
 Extending our ISA

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 Extending our instruction set

For MARIE, we have seen only 9 instructions while we have 4

bits, so we can have 16 different instructions.
We will now extend our ISA by adding 4 new instructions: JnS,
Clear, AddI and JumpI

Memorize
this table!

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 Extending our instruction set

 JnS: Jump-and-Store instruction

• Allows us to store a pointer and then proceeds to set the PC to a different
instruction
• This enables us to call procedures and other subroutines, and then return to
the calling point in our code once the subroutine has finished.
 Clear:
• This instruction moves all zeros into the accumulator.
• This saves the machine cycles that would otherwise be expended in loading a
0 operand from memory.
JnS RTL Clear RTL
MBR ← PC AC ← 0
MAR ← X
M[MAR] ← MBR
MBR ← X
AC ← 1
AC ← AC + MBR
PC ← AC

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 Extending our instruction set

So far, all of the MARIE instructions that we have discussed

use a direct addressing mode.
This means that the address (not the value!) of the
operand is explicitly stated in the instruction.
It is often useful to employ an indirect addressing:
- The address of the address of the operand is given in the
instruction.
- This means that the content of the given address is the
address of the needed value.

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 Extending our instruction set

 JumpI and AddI use indirect addressing

 Their RTL are shown in the table below

JumpI RTL AddI RTL

MAR ← X MAR ← X
MBR ← M[MAR] MBR ← M[MAR]
PC ← MBR MAR ← MBR
MBR ← M[MAR]
AC ← AC + MBR

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 FOR NEXT LECTURE (1/1)

 Exercise:
1. Write a program that calculates 2X + Y - Z where
X, Y, Z are three different numbers in three
different memory locations. Store the result in
the main memory and display it.
2. Implement your code in MARIE simulator.
3. Check if you have errors.
4. Correct your errors and run your program.

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 End of chapter 4
Try to solve all exercises related to chapter 4.
Download MARIE Simulator

Use the simulator to write and run your own

assembly programs!