Hardware Description

Languages

Professor: Sci.D., Professor

Vazgen Melikyan

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Course Overview

 The Role and Classification of HDLs

 1 lecture
 System Verilog
 2 lectures
 SystemC
 3 lectures
 Verilog
 4 lectures
 VHDL
 3 lectures
 Process of Synthesis
 2 lectures

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System Verilog

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Classification of System Level
Languages
 System-Level Language
 C/C++Based
 System C
 Cynlib
 SoC++
 Handel-C
 A/RT (Library)
 VHDL/VERILOG Replacements
 VHDL+
 System Verilog
 Higher-level Language
 SDL
 Entirely New Language
 SLDL
 SUPERLOG
 Java-Based
 JAVA

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Overview

 System Verilog
 Definition of System Verilog
 Main features of System Verilog
 System Verilog differences from other languages

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System Verilog Description

 System Verilog description

 Hardware description and Verification language
(HDVL)
 Set of enhancements to IEEE 1364 Verilog-2001
standards
 Features inherited from Verilog HDL,VHDL,C,C++
 Extended features to Verilog

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Advantages of System Verilog

 System Verilog
 Constrained Randomization
 OOP support
 Assertions
 Narrow gap b/w design & verification engineer
 Coverage support
 New data types like logic
 Easy C model integration

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Data Types

 Bit data
 String
 Arrays
 Dynamic arrays
 Queue
 Associative Arrays
 New types
 Struct
 Union
 Enumerated
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Data Types: Bit Data

Type Definition Example

reg 4-state Verilog-2001 reg r;
logic 4-valued logic logic w;
bit 2-state bit 0 or 1 bit b;
integer 4-state, 32-bits, signed Verilog-2001 integer I;
byte 8 bit signed integer byte b8;
int 2-state, 32-bit signed integer int i;
shortint 2-state, 16-bit signed integer shortint s;
longint 2-state, 64-bit signed integer longint l;

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Data Types: String

Operations
 Contains a variable
standard Verilog operators
length array of ASCII
len()
characters. Each time substr()
a value is assigned to putc(), getc()
the string, the length toupper(), tolower()
of the array is compare(), icompare()
automatically atoi(), atohex(), atooct(), atobin(),
atoreal()
adjusted. itoa(), hextoa(), octtoa(), bintoa(),
realtoa()

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Data Types: Dynamic Arrays
Array size Operator for
Declaration Example
giving space allocation
With empty During Run time new[ ] int arr[ ], arr1[ ];
word initial begin
subscripts [ ].
arr = new[5];
foreach (arr[j])
arr[j] = j;
arr1 = arr;
arr1[0] = 5;
$display(arr[0], arr1[0]);
arr = new[20](arr);
arr = new[100];
arr.delete;
End
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Data Types: Queues

int j = 1,
b[$] = {3,4},
q[$] = {0,2,5};
initial begin
q.insert(1, j);
q.insert(3, b);
q.delete(1);
q.push_front(6);
j = q.pop_back;
q.push_back(8);
j = q.pop_front;
foreach (q[i])
$display(q[i]);
end

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Data Types: Associative Arrays
Name Declaration Example
Associative Arrays one-dimensional sparse initial begin
arrays that can be used logic [63:0] assoc[*], idx = 1;
as index enumerated
type names repeat (64) begin
assoc[idx] = idx;
idx = idx << 1;
end
foreach (assoc[i])
$display(“assoc[%h] = %h”, i, assoc[i]);
if (assoc.first(idx)) begin
do
$display(“assoc[%h] = %h”, i, assoc[idx]);
while (assoc.next(idx));
end
assoc.first(idx);
assoc.delete(idx);
end

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Array Reduction Methods

 Basic methods Example

 Reduces array bit on[10];

int summ;
to a scalar initial begin
foreach (on[i])
on[i] = i;
$display(“on.sum = %0d”, on.sum);
summ = on.sum;
$display(“summ = %0d” , summ);
if (on.sum >=32'd5)
$display(“sum has more than 5
1's”);
end

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New Type Creation

 New type creation

 Verilog
 `define OP 8
 `define OPR reg [`OP-1:0]
 ` OPR op_a, op_b;
 System Verilog
 parameter OP = 8;
 typedef reg [OR-1:0] op_t;
 op_t op_a, op_b;

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New Type: Struct

Syntax Example
typedef struct typedef struct
{data_type var1,var2,var3;} {bit [7:0] r, g, b;}
struct_name; pixel_s;

struct_name variable_name; pixel_s my_pixel;

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New Type: Union

Syntax Example
typedef union
typedef union
{data_type var1;} un_name; {int i; real f;} num_u;

un_name var; num_u un;

un.f = 0.0;
var.f = 0.0;

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Data Types: Enumerated Data

Syntax Example

typedef enum
typedef
{name1, name2, …} enum _name; enum {RED, BLUE, GREEN} color;

enum _name var; color col;

var = name1; col = BLUE;

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Routines For Enumerated Types

 Routines for enumerated types

 First
 Returns first member of the enumeration
 Last
 Returns last member of the enumeration
 Next
 Returns the next element of the enumeration
 Next (N)
 Returns the N next element
 Prev
 Returns the previous member of the enumeration
 Prev (N)
 Returns the N previous element
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Statements

 Statements
 Procedural statements
 Continue and break statement

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Procedural Statements

Example
 Procedural
Initial
statements begin: example
 The increment ++ and integer array[10], sum, j;
for (int i = 0; i<10; i++)
decrement – operators
array[i] = I;
are available in both sum = array[9];
pre and post form j = 8;
do
 Label on a begin or
sum+= array[j];
fork statement can be while (j--);
put on thematching $display (“Sum=%4d”,sum);
end or join statement end:example

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Continue and Break Statement

 Continue and break Example

statement initial begin

logic [127:0] cmd;
 Continue integer file, c;
file = $fopen(“commands.txt”, “r”);
 Skip over rest of the while (!$feof(file)) begin
statements in a loop c = $fscanf(file, “%s”, cmd);
case (cmd)
 Break “”: continue;
 Leave loop immediately “done”: break;
……
endcase
end
$fclose(file);
end

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Task and Function Overview

Example
 Improvement
 Begin..end are task mult_line;
optional, task/endtask, $display(“First line”);
function/endfunction $display(Second line”);
are enough to define endtask: mult_line
the routine boundaries

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Routine Arguments

 Routine arguments
 Verilog
 Declare arguments twice, once for direction and once for type
 System Verilog
 Declare arguments once

C-style routine argument

task mytask1(output logic [31:0] x,

input logic y);
……..
endtask

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Advanced Argument Type

 ref Example

 Can be specified, the function void print (const ref

int a[]);
argument is passed by int sum = 0;
reference rather then for (int I =0 ; i<a.size; i++)
copying its value begin
sum += a[i];
 Array can be passed $display(“The sum of the array
into a routine is “, sum);
endfunction

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Returning From A Routine

 Return statement makes it easier to control

the flow in routines.
Return in a task

task load(int len, ref int array[]);

if (len <= 0) begin
$display(“Bad len”);
return;
end
……
endtask

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Automatic Storage

Example
 Routines storage
program automatic test;
 Default task wait_f( input [31:0]
 Static for module and addr, expext_data, output
program success );
while (bus.addr !== addr)
 User defined
@(bus.addr);
 Automatic for program,
success = (bus.data ==
with keyword automatic expect_data);
endtask
…..
endprogram

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Time Unit and Precision

 Time unit and precision Example

 Timescale module timing;

timeunit 1ns;
 Files must be compiled in a
timeprecision 1ps;
proper order to be sure that
initial begin
all delays used proper scale
$timeformat(-9, 3, “ns”, 8);
and precision #1 $display(“@%t”, $realtime);
 Timeunit #2ns $display(“@%t”, $realtime);
#0.1ns $display(“@%t”, $realtime);
 Timeprecision
#41ps $display(“@%t”, $realtime);
 Specifying for every end
module endmodule

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OOP Terminology

 Class
 Basic building block containing routines and variables. The analogue in Verilog is
a module.
 Prototype
 The header of the routine that shows the name, type, and argument list.
 Method
 The procedural code that manipulates variables, contained in tasks and functions.
 Handle
 A pointer to an object.
 Object
 An instance of a class. In Verilog a module must be instantiated to use it.
 Property
 A variable that holds data.
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Classes

 Data declarations
 Tasks and functions for operating on the data
 Verification routines and highly abstract system-level modeling.
 Dynamic nature: ideal for testbench modeling. Not Synthesizable
 Memory allocation, de-allocation and garbage collection are
automatically handled.
 Dynamically created, deleted and assigned values. Objects can be
accessed via handles, which provide a safe form of pointers.
 Classes can have inheritance and public or private protection, as in
C++.

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Class Example
class Packet;
bit [3:0] command;
bit [39:0] address;
bit [4:0] master_id;
integer time_requested;
integer time_issued;
integer status;

function new();
command = 4’hA;
address = 40’hFE;
master_id = 5’b0;
endfunction

task clean () ;
command = 4’h0; address =
40’h0;
master_id = 5’b0;
endtask
endclass

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One Class Inside Another

class Bustran;
bit [31:0] addr, crc, data[8];
Statistics stats;
endclass

class Statistics;
time startT, stopT;
static int ntrans = 0;
static time total_elapsed_time;
endclass

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Compilation Order Issue

 To prevent problems Example

related with included typedef class Statistics;

class Bustran;
class use as new Statistics stats;
type, classes must be …..
endclass
declared with typedef
statement. class Statistics;
…….
endclass

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 Verification Environment
Testbench
Checks Verification
correctness Environment
Creates
stimulus
Identifies
Test Self Check transactions
Executes
transactions

Transactor Checker
Observes
Supplies data data
to the DUT from DUT
Driver Assertions Monitor

DUT

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Communication With Ports

Example
 Arbiter model using module arb_port (output logic [1:0]
ports grant,
input logic [1:0] request,
input logic reset,
input logic clk);
......
always @(posedge clk or posedge
reset) begin
if (reset)
grant <= 2'b00;
else
…
end
endmodule

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Communication With Ports (2)

 Testbench using ports Example

Module test (input logic [1:0] grant,
Output logic [1:0] request,
Output logic reset,
Input logic clk);
Initial begin
@(posedge clk) request <=2'b01;
$diplay(“@%0d: Drove req =01”, $time);
Repeat (2) @(posedge clk);
If (grant != 2'b01)
$display(“@%0d: a1: grant != 2'b01”,
$time);
.....
$finish;
End
endmodule

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Communication With Ports (2)

Example
 Top-level netlist Module top;
without an interface Logic [1:0] grant, request;
Logic clk =0,reset;
Always #5 clk=~clk;
arb_port a1
(grant,request,reset,clk);
Test t1(grant, request, reset, clk);
endmodule

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Interfaces

 Several modules often have many of the

same ports
 Prevent Redundancy in code
 Can include functionality & built-in protocol
checking
 The variables and nets in it are assumed to
be inout ports
 Abstraction
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Interface Example

interface simple_bus; // Define the module cpuMod(simple_bus b, input

interface bit clk);
logic req, gnt; ...
logic [7:0] addr, data; endmodule
logic [1:0] mode;
logic start, rdy;
endinterface: simple_bus module top;
logic clk = 0;
module memMod(simple_bus a, // Use the simple_bus sb_intf; //
simple_bus interface Instantiate the interface
input bit clk); memMod mem(sb_intf, clk);
logic avail;
cpuMod
// a.req is the req signal in the
’simple_bus’ interface cpu(.b(sb_intf), .clk(clk));
always @(posedge clk) a.gnt <= a.req & endmodule
avail;
endmodule

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Interface Example (2)

Interface serial(input bit task read(output data_type

clk); d);
logic data_wire; while (data_start !== 1)
logic data_start=0; @(negedgeclk);
task write(input data_type d); for (inti = 0; i <= 31; i++)
for (int i = 0; i <= 31; i++) begin
begin d[i] <= data_wire;
if (i==0) data_start <= 1; @(negedgeclk) ;
else data_start <= 0;
end
data_wire = d[i];
endtask
@(posedge clk) data_wire = 'x;
endinterface
end
endtask

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Grouping Signals In An Interface
Using Modports
 The modport Example

construct allows interface arb_if(input bit

clk);
grouping signals and logic [1:0] grant, request;
logic reset;
specifying directions modport TEST (output request,
reset,
input grant, clk);
modport DUT (input request,
reset, clk,
output grant);
modport Monitor (input request,
grant, reset,clk);
endinterface

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The Advantages of Using An
Interface
 An interface is ideal for design reuse. When two blocks
communicate with a specified protocol using two or more signals, an
interface is used. If signals are repeated over and over, as in a
networking switch, a virtual interface is used.
 The interface takes the jumble of signals that is declared over and
over in every module or program and puts it in a central location
reducing the possibility of misconnecting signals.
 To add a new signal, it just needs to be declared once in the
interface not in higher-level modules once again reducing errors.
 Modports allow a module to easily tap a subset of signals from an
interface. Signal direction for additional checking can be specified.

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The Disadvantages of Using An
Interface
 For point-to-point connections, interfaces with modports are almost
as verbose as using ports with lists of signals. But all the
declarations are still in one central location, reducing the chance for
making an error.
 The interface name must be used in addition to the signal name
possibly making the modules more verbose.
 If two design blocks are connected with a unique protocol that will
not be reused, interfaces may be more work than just wiring
together the ports.
 It is difficult to connect two different interfaces. A new interface may
contain all the signals of an existing one plus new signals. But since
interfaces cannot be hierarchical, the individual signals must be
broken out and driven appropriately.
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Clocking Block

 Specify synchronization characteristics of the

design
 Offer a clean way to drive and sample signals
 Features
 Clock specification
 Input skew,output skew
 Cycle delay (##)

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Clocking Block (2)
Module M1(ck, enin, din, enout, dout);
input ck,enin;
input [31:0] din ;
output enout ;
output [31:0] dout ;

Signals will be sampled 2ns

clocking sd @(posedge ck);
before posedge ck
input #2ns ein,din ;
output #3ns enout, dout;
endclocking:sd

Signals will be driven 3ns after

reg [7:0] sab ; posedge ck
initial begin
sab = sd.din[7:0];
end
endmodule:M1

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Assertions

 Special language constructs to verify design

behavior; a statement that a specific
condition, or sequence of conditions, in a
design is true.
 For documentation of the assumptions
 Assertions outside of Verilog modules
 Very complex combination of situations

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Assertion Types

 Concurrent
 The property must be true throughout a simulation
 Procedural
 Incorporated in procedural code
 Apply only for a limited time

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Procedural Assertions

 Immediate
 At the time of statement execution
 Strobed
 Schedule the evaluation of the expression for the end
of current timescale to let the glitches settle down
 Clocked
 Triggered by an event or sampling clock

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Immediate Assertions

 Severity level
 $info
 $warning
 $fatal : terminates the simulation with an error code. The first
argument shall be consistent with the argument to $finish
 $error
 assert (myfunc(a,b)) count1 = count + 1; else -
>event1;
 [ identifier : ] assert ( expression )
[ pass_statement ] [ else fail_statement ]
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Strobed Assertions

Example
 If immediate assertion is
triggered by a timing control always @(posedge clock)
that happens at the same time a = a + 1; // blocking
as a blocking assignment to assignment
the data being tested, there is always @(posedge clock)
a risk of the wrong value being begin
sampled. ...
 Pass and Fail statements in assert (a < b);
strobed assertions must not cas:assert_strobe (a <
create more events at that time b);
slot or change values. end

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System Functions

 $onehot
 (<expression>) returns true if only one and only one bit of expression is high
 $onehot0
 (<expression>) returns true if at most one bit of expression is low
 $inset
 (<expression>, <expression> {, <expression> } ) returns true if the first expression
is equal to at least one of the subsequent expression arguments
 $insetz
 (<expression>,<expression> {, <expression> } ) returns true if the first expression
is equal to at least other expression argument
 $isunknown
 (<expression>) returns true if any bit of the expression is ‘x’

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Assertion Example

Example
 A sequence of
sequence request_check;
conditions that spans
request ##[1:3]
multiple clock cycles grant ##1 !request
##1 !grant;
endsequense

always @(posedge clock)

if (State == FETCH)
assert request_check;

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Randomization

 Benefits of randomization
 Random generation of stimulus
 Random setting of parameters
 Hard-to-reach corner cases can be reached

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Randomization (2)

 Shift from directed to random

 Directed
 Detect the expected bugs
 Time consuming
 Random
 Detects unexpected bugs
 Tremendously reduce the efforts

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Randomization (3)

 Constrained randomization
 Improves the result
 Speeds-up the bug finding process
 More interesting cases can be achieved within the
constrained boundary

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 Synopsys University Courseware
Copyright © 2014 Synopsys, Inc. All rights reserved.
Hardware Description Languages
Lecture - 2
Developed By: Vazgen Melikyan
56