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Chapter 4 - Design and Analysis

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0% found this document useful (0 votes)
109 views17 pages

Chapter 4 - Design and Analysis

Uploaded by

Bismah Asif
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital Logic Design

Chapter 4
Combinational Logic

Digital Design: With an Introduction to the Verilog HDL, 5e Copyright ©2013 by Pearson Education, Inc.
M. Morris Mano • Michael D. Ciletti All rights reserved.
Types Of Digital Systems

• Combinational Logic:
Output depends on the present input combination

No information of previous output :i.e No storage involved


• Sequential Logic:
Output depends on the present input as well as previous output
Storage involved.
It will be covered in chapter 5
Amina Asif,
Digital Design: With an Introduction to theSpring 2020.
Verilog HDL, 5e
2
Copyright ©2013 by Pearson Education, Inc.
M. Morris Mano • Michael D. Ciletti All rights reserved.
Digital Design: With an Introduction to the Verilog HDL, 5e Copyright ©2013 by Pearson Education, Inc.
M. Morris Mano • Michael D. Ciletti All rights reserved.
Procedures in Combinational Systems

1. Design Procedure
2. Analysis Procedure

• Design
 Boolean Expression is given by some means mostly one
comprehensive statement
 Figure out the logic diagram.

• Analysis
 Logic diagram is given
 Figure out the Boolean Equation
Amina Asif,
Digital Design: With an Introduction to theSpring 2020.
Verilog HDL, 5e
4
Copyright ©2013 by Pearson Education, Inc.
M. Morris Mano • Michael D. Ciletti All rights reserved.
Amina Asif,
Digital Design: With an Introduction to theSpring 2020.
Verilog HDL, 5e
5
Copyright ©2013 by Pearson Education, Inc.
M. Morris Mano • Michael D. Ciletti All rights reserved.
Design Procedure

• Try to understand the design statement.


• Identify the number of inputs and outputs
and label them appropriately
• Draw the truth table according to the
design statement.
• Get the simplified output expression using
K-maps. We will have K-maps for all the
outputs.
• Draw the logic diagram of the obtained
output expression.
Amina Asif, Spring 2020. 6
Digital Design: With an Introduction to the Verilog HDL, 5e
M. Morris Mano • Michael D. Ciletti
Copyright ©2013 by Pearson Education, Inc.
All rights reserved.
Design Examples

1. Design a 4-bit Binary to BCD converter.

2. Design a 4-bit Gray-Code to Binary-Code


converter.

3. Design a car buzzer that turns on


whenever a door is open or the seat belt
is not buckled when the key is in ignition.
If the key is not in ignition, we shouldn’t
have to worry about seat belt.
Amina Asif, Spring 2020. 7
Digital Design: With an Introduction to the Verilog HDL, 5e
M. Morris Mano • Michael D. Ciletti
Copyright ©2013 by Pearson Education, Inc.
All rights reserved.
Design Example

Design a car security system that has


buzzer which gets ON whenever door is
open OR the key is in the ignition AND the
seat belt is not buckled.

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Digital Design: With an Introduction to theSpring 2020.
Verilog HDL, 5e
8
Copyright ©2013 by Pearson Education, Inc.
M. Morris Mano • Michael D. Ciletti All rights reserved.
Design Procedure :Step 2

• From the specifications of the circuit,


determine the required number of inputs
and outputs and assign a symbol to
each
Identify the inputs and outputs
jk Car
security

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Digital Design: With an Introduction to theSpring 2020.
Verilog HDL, 5e
9
Copyright ©2013 by Pearson Education, Inc.
M. Morris Mano • Michael D. Ciletti All rights reserved.
Design Procedure :Step 3

• Obtain the simplified Boolean functions for


each output as a function of the input
variables.
• For that you need to draw the truth table
according to given conditions

Amina Asif,
Digital Design: With an Introduction to theSpring 2020.
Verilog HDL, 5e
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Copyright ©2013 by Pearson Education, Inc.
M. Morris Mano • Michael D. Ciletti All rights reserved.
Step 3: Getting the Truth Table and Logic
equations

D=1 when Door is open, D=0 when Door is closed


I=1 when Ignition is on, I=0 when ignition is off
S=1 when seat belt buckled, S=0 when not
buckled D I S B
0 0 0 0
Truth Table: 0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
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Digital Design: With an Introduction to theSpring 2020.
Verilog HDL, 5e
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Copyright ©2013 by Pearson Education, Inc.
M. Morris Mano • Michael D. Ciletti All rights reserved.
Step 3 (cont’d)expression

• Use K-Map

• Simplified expression: B=D+IS’

Amina Asif,
Digital Design: With an Introduction to theSpring 2020.
Verilog HDL, 5e
12
Copyright ©2013 by Pearson Education, Inc.
M. Morris Mano • Michael D. Ciletti All rights reserved.
Design Procedure :Step 4

• Draw the logic diagram and verify the


correctness of the design (manually or by
simulation).

Amina Asif,
Digital Design: With an Introduction to theSpring 2020.
Verilog HDL, 5e
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Copyright ©2013 by Pearson Education, Inc.
M. Morris Mano • Michael D. Ciletti All rights reserved.
Half Adder

A half adder is circuit that takes two inputs


x and y one bit each, it gives the sum of
these two inputs as its output.
Example:

Amina Asif,
Digital Design: With an Introduction to theSpring 2020.
Verilog HDL, 5e
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Copyright ©2013 by Pearson Education, Inc.
M. Morris Mano • Michael D. Ciletti All rights reserved.
Truth Table and Logic Equation Of Half Adder

• Logic Equation

Amina Asif,
Digital Design: With an Introduction to theSpring 2020.
Verilog HDL, 5e
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Copyright ©2013 by Pearson Education, Inc.
M. Morris Mano • Michael D. Ciletti All rights reserved.
Logic Diagram

Amina Asif,
Digital Design: With an Introduction to theSpring 2020.
Verilog HDL, 5e
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Copyright ©2013 by Pearson Education, Inc.
M. Morris Mano • Michael D. Ciletti All rights reserved.
Practice Problems

• Solve end of chapter problems


(4.4, 4.5, 4.6)

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Digital Design: With an Introduction to theSpring 2020.
Verilog HDL, 5e
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Copyright ©2013 by Pearson Education, Inc.
M. Morris Mano • Michael D. Ciletti All rights reserved.

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