Project Phase-2 Zeroth Review

on
Design of Efficient BCD Adder Using Different Logic Gates
Presented By
19691A04G4 – M. SAI KIRAN
19691AO4G6 – K. SAI SANDEEP RAJU
19691AO4I4 – CH. SIVA KUMAR
Guided by
Dr. RAJ KUMAR
(Asst. Professor)
Department of Electronics and Communication Engineering
MADANAPALLE INSTITUTE OF TECHNOLOGY AND SCIENCE
MADANAPALLE
(UGC-AUTONOMOUS)
 Outline
• Abstract
• Introduction
• Objectives
• Literature review
• Existing Method
• Analysis
• Result Analysis and Comparison
• Future Work
• References
 ABSTRACT

Many new approaches are capable of natively realizing majority-of-three (MAJ) gates. There
are several effective XOR designs that are directly derived from the physical properties of new
approaches, even though improved gates like exclusive-OR (XOR) gates may be accomplished
using various MAJ gates.
In this paper, we introduced multi-digit exclusive-OR (XOR3) and MAJ adder designs for
binary coded decimal (BCD) adders with three inputs. In computers for business, industry, and
finance, BCD adder is frequently used.
After developing Verilog code to implement the designs, we used the Xilinx Vivado tool to
simulate and synthesize the designs. Various binary adders, such the RCA-BCD and PBA-BCD
adders, are used to validate the suggested logic representations.
The addition of XOR3 gates makes it possible to create compact logic representations, which
has a good impact on both area and latency. The suggested 1-digit BCD adder has reduced area
and delay when compared to the best current designs.
 INTRODUCTION
A 4-bit binary adder known as a "BCD adder" can add two 4-bit words in the BCD format as
shown in Fig 1.1. A 4-bit output word in BCD format is the addition output. It can describe the
decimal sum of the addend and augend as well as the carry that is produced if this total is
greater than nine. As a result, BCD adders can add decimals. BCD adder is a circuit that
simultaneously adds two BCD digits and generates a BCD sum digit.
The corrective logic should be built into a BCD adder's internal design. We utilize a second 4-
bit binary adder to add 0110 to the binary sum. The top 4-bit binary adder first adds the two
decimal digits and the input-carry to create the binary sum. Nothing is added to the binary sum
when the output-carry is the same as 0. The bottom 4-bit binary adder inserts binary 0110 into
the binary total when the value is equal to 1. Because the output-carry produced by the lowest
binary adder provides data that is already available in the output-carry terminal, it may be
refused.
BCD adder phases are needed for a decimal parallel adder that adds n decimal digits, with the
input-carry of one phase being linked to the output-carry of the next higher order stage. The
required circuits for carrying look-ahead are included in BCD adders to reduce propagation
delays. Additionally, not all four full-adders are required in the adder circuit for the correction,
and this circuit can be improved.
 OBJECTIVES

To reduce the delay of the adder

To reduce the area requirement
To reduce the hardware complexity
 LITERATURE REVIEW

M. Taghizadeh, M. Askari, and K. Fardad, 2008 [1]. The BCD adder structural layout,
binary coded decimal (BCD) is a method of encoding decimal values in computer and
electrical systems where each digit is represented by a unique binary sequence. Despite of
its limitations in efficient encoding and the requirement for more complicated circuits to
accomplish mathematical operations. It is less frequently utilized in commercial, industrial,
and financial applications. It can add in binary format before doing the conversion to BCD
in order to accomplish addition in BCD. In this conversion, each group of four digits with a
value more than 9 needs to have a value of added 6 to it. In addition to a conversion, it is
used two four-bit binary adders. Ripple carry adder is the binary adder. Five separate clock
zones, three majority voter (MV) gates, two invertors, and a synchronous complete adder
make the device. For a half adder and a full adder, the corresponding equations are
employed.
 Cont…
G. Cororullo, P. Corsonello, F. Frustaci, and S. Perri, 2017 [2]. The adder uses 1196
cells in a total size of just 1.36 m2 and completes its generic operation in 14 clock phases
(or 3 clock cycles). The 2D clocking scheme's distinct partitioning technique results in some
delay and space overheads, but this is a tolerable price to pay for the clock circuitry's
simplicity and increased feasibility. Nevertheless, it would be realistic to anticipate similar
effects on performance and area if the carry flag adder (CFA) and carry lookahead adder
(CLA) based counter parts are achieved using the 2D clocking technique. The proposed
unconventional logic formulations and specially created logic modules enable
outperforming published literature decimal adders. The computational delay and space
occupancy of the new 1-digit BCD adder are up to 36% and 52% lower than those of its
competitors, respectively. When two n-digit decimal numbers must be added, these benefits
are considerable. The proposed design for a two-digit adder operates in just 18 clock phases
and takes up approximately 2.74 m2. Finally, a more workable implementation of the new
adder has been produced without sacrificing the benefits attained over its direct rivals by
taking advantage of the 2-D wave clocking technique.
 Cont…
D. Abedi, and G. Jaberipur, 2018 [3]. As CMOS replacements, new developing
technologies with low area/power/latency characteristics are gaining traction. In particular,
numerous arithmetic circuits have been reconfigured for the realization of quantum dot
cellular automata. Three-way majority gates and inverters are the fundamental components
of a quantum dot cellular automaton. By directly replacing AND and OR gates with
partially utilized majority (PUM) gates (i.e., with a "0" and "1" input, respectively), logical
circuits can be trivially mapped to their equivalents in quantum dot cellular automata,
allowing for the exploitation of the fundamental building blocks of these systems. For
instance, using the afore mentioned direct mapping, numerous quantum dot cellular
automata decimal complete adders are easily created. Only one proposal, however,
substitutes numerous AND and OR gates with PUMs while attempting to make better use of
majority gates. In this study, we present a quantum dot cellular automata decimal complete
adder that mostly consists of fully utilized majority gates (i.e., without constant inputs) and
infrequently contains PUMs. The cell count, area, and delay of the suggested circuit
demonstrate improvements of 39%, 78%, and 12%, respectively, when compared to
comparable prior efforts, after being designed and evaluated by a quantum dot cellular
automata designer.
 Cont…
T. Zhang, V. Pudi, and W. Liu, 2019 [4]. The definition of output decimal carry is to
include majority gates and suggested a carry lookahead mechanism for computing all
intermediate output carries. This approach was taken when building the multi-digit decimal
adders. The latency and area-delay product (ADP) are theoretically 50% lower with our best
n-digit decimal adder design compared to earlier designs. Using a tool called the quantum
dot cellular automata designer, we put our plans into practice. In comparison to the best
current designs, the suggested 8-digit PBA-BCD adder achieves about 38% shorter delay. It
is based on quantum dot cellular automata designer. The multi-digit BCD adders carries are
computed in parallel using a novel concept for BCD adder output carry computation in
terms of majority gates. To calculate carries in the BCD adder, we have implemented
decimal group generate and decimal group propagate signals. As a result, the multidigit
BCD adder now runs faster. The suggested multi-digit BCD adder was implemented using a
variety of binary adders, including RCA, CFA, and parallel binary adder (PBA). In
comparison to previous designs, our PBA-based n-digit BCD adder theoretically reduces
delay and area-delay product (ADP) by 50%.
 Cont…
G. Saida, and S. Meena, 2016 [5]. The most crucial aspect of VLSI design is lowering the
device power consumption. The low power, full voltage swing BCD addition employing a
gate diffusion input cell is the topic of this research. When compared to traditional BCD
adders, the average power of the suggested BCD adder is 10.2793 Watt, while the average
power of conventional BCD adders is 50.4721 Watt. As a result, the suggested circuit
consumes 80% less power. Additionally, space and speed are maximized. In digital circuits,
a buffer is used to obtain the complete voltage swing, or full logic levels of logic "1" and
"0." And using UMC65 nm technology, the circuit designing and modelling were carried
out. Gate Diffusion Input Cell is used to implement the suggested BCD adder. Although
gate diffusion input (GDI) cells resemble CMOS inverters, they have three input terminals
instead of two. It is possible to create logic circuits like AND, OR, inverters, and MUX
using gate diffusion input cells.
 EXISTING METHOD

In this chapter, some important literature on BCD adder is given below.

Zhufei Chu, Zeqiang Li, Yinshui Xia, Lunyao Wang, and Weiqiang Liu, 2017. The
schematic of 1-digit RCA-BCD adder, which consists of two 4-bit binary adders, named ADD1
and ADD2, and a correction logic (CL) circuit. Given two BCD numbers dA3:0 and dB3:0,
along with dCin, the ADD1 adds them to produce the binary sum bS3:0 and output carry
bCout. The CL circuit is used to correct the BCD sum output if bS3:0 ≥ 10. It produces the
cL3:0 and decimal output carry signal dCout. The cL3:0 is (0110)2 if dCout = 1. Otherwise,
cL3:0 is (0000)2. The ADD2 adds bS3:0 and cL3:0 to obtain decimal sum dS3:0. As shown in
Fig, a carry-lookahead structure is proposed in [5] for calculating the output carries, which was
employed into the designs of multi-digit BCD adders based on parallel implementation.
Moreover, a new structure was presented in the CL circuit, where dCin served as an extra input.
As a result, the delay required for dCout has been significantly reduced for multi-digit BCD
adder.
 Cont…

Fig 1. BCD Adder (a) Existing (b) Proposed [4]

 Cont…
Disadvantages of Existing System
Delay is very high
Area requirement is high
Circuit complexity is high
 ANALYSIS

The comparison of logic circuits of the proposed work and existing work can be compared
using unit gate model (UGM).
Unit Gate Model (UGM)
In this model, two-input digital logic gates (AND, OR, NAND, NOR) are assumed with
the delay and area of one unit.
The exclusive gates(XOR, XNOR) require the delay and area of two units, whereas the
area and delay of NOT gate are counted as zero.
 Cont…

1 1

Fig 2. UGM Analysis for Logic Gates

 RESULT ANALYSIS AND COMPARISON

Different Adders Number of bits Area (Unit area) Delay (Unit delay) ADP(Area Delay
product)
4 60 35 2100
Existing
8 120 70 8400
12 180 105 18900
16 240 140 33600
4 60 35 2100
[4]
8 120 70 8400
12 180 105 18900
16 240 140 33600
 FUTURE WORK

 As the results compared between the existing work and [4] is done. By using the approximate
analysis method named UGM (Unit Gate Model). We are not proposed any work in project
phase1

 Now in project phase2, We are going to design BCD adder using parallel prefix adder (PPA). By
using parallel prefix adder, we can reduce the delay and area of this BCD adder.
 REFERENCES

[1] M. Taghizadeh, M. Askari, and K. Fardad, “BCD computing structures in quantum—Dot cellular
automata,” in Proc. Int. Conf. Comput. Commun. Eng., Kuala Lumpur, Malaysia, 2008, pp. 1042–
1045.
[2] G. Cocorullo, P. Corsonello, F. Frustaci, and S. Perri, “Design of efficient BCD adders in
quantum-dot cellular automata,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 64, no. 5, pp. 575–
579, May 2017.
[3] D. Abedi and G. Jaberipur, “Decimal full adders specially designed for quantum-dot cellular
automata,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 65, no. 1, pp. 106–110, Jan. 2018.
[4] T. Zhang, V. Pudi, and W. Liu, “New majority gate-based parallel BCD adder designs for
quantum-dot cellular automata,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 66, no. 7, pp. 1232–
1236, Jul. 2019.
[5] G. Saida and S. Meena, “Implementation of low power BCD adder using gate diffusion input
cell,” in Proc. Int. Conf. Commun. Signal Process., Melmaruvathur, India, 2016, pp. 1352–1355.
THANK YOU