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29 views15 pages

Reading Assignment1

Uploaded by

Udai Valluru
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Computer Architecture

A Quantitative Approach, Fifth Edition

Chapter 3
Instruction-Level Parallelism
and Its Exploitation

Copyright © 2012, Elsevier Inc. All rights reserved. 1


Dynamic Scheduling, Multiple Issue, and Speculation
Dynamic Scheduling, Multiple Issue, and Speculation

 Modern microarchitectures:
 Dynamic scheduling + multiple issue +
speculation

 Two approaches:
 Assign reservation stations and update
pipeline control table in half clock cycles
 Only supports 2 instructions/clock
 Design logic to handle any possible
dependencies between the instructions
 Hybrid approaches

Copyright © 2012, Elsevier Inc. All rights reserved. 2



Dynamic Scheduling, Multiple Issue, and Speculation
Overview of Design

Copyright © 2012, Elsevier Inc. All rights reserved. 3


Dynamic Scheduling, Multiple Issue, and Speculation
Multiple Issue
 Limit the number of instructions of a given
class that can be issued in a “bundle”
 I.e. on FP, one integer, one load, one store

 Examine all the dependencies amoung the


instructions in the bundle

 If dependencies exist in bundle, encode


them in reservation stations

 Also need multiple completion/commit


Copyright © 2012, Elsevier Inc. All rights reserved. 4
Dynamic Scheduling, Multiple Issue, and Speculation
Example
Loop: LD R2,0(R1) ;R2=array element
DADDIU R2,R2,#1 ;increment R2
SD R2,0(R1) ;store result
DADDIU R1,R1,#8 ;increment pointer
BNE R2,R3,LOOP ;branch if not last element

Copyright © 2012, Elsevier Inc. All rights reserved. 5


Dynamic Scheduling, Multiple Issue, and Speculation
Example (No Speculation)

Copyright © 2012, Elsevier Inc. All rights reserved. 6


Dynamic Scheduling, Multiple Issue, and Speculation
Example

Copyright © 2012, Elsevier Inc. All rights reserved. 7


Adv. Techniques for Instruction Delivery and Speculation
Branch-Target Buffer
 Need high instruction bandwidth!
 Branch-Target buffers
 Next PC prediction buffer, indexed by current PC

Copyright © 2012, Elsevier Inc. All rights reserved. 8


Adv. Techniques for Instruction Delivery and Speculation
Branch Folding
 Optimization:
 Larger branch-target buffer
 Add target instruction into buffer to deal with
longer decoding time required by larger buffer
 “Branch folding”

Copyright © 2012, Elsevier Inc. All rights reserved. 9


Adv. Techniques for Instruction Delivery and Speculation
Return Address Predictor
 Most unconditional branches come from
function returns
 The same procedure can be called from
multiple sites
 Causes the buffer to potentially forget about
the return address from previous calls
 Create return address buffer organized
as a stack

Copyright © 2012, Elsevier Inc. All rights reserved. 10


Adv. Techniques for Instruction Delivery and Speculation
Integrated Instruction Fetch Unit
 Design monolithic unit that performs:
 Branch prediction
 Instruction prefetch
 Fetch ahead
 Instruction memory access and buffering
 Deal with crossing cache lines

Copyright © 2012, Elsevier Inc. All rights reserved. 11


Adv. Techniques for Instruction Delivery and Speculation
Register Renaming
 Register renaming vs. reorder buffers
 Instead of virtual registers from reservation stations and
reorder buffer, create a single register pool
 Contains visible registers and virtual registers
 Use hardware-based map to rename registers during issue
 WAW and WAR hazards are avoided
 Speculation recovery occurs by copying during commit
 Still need a ROB-like queue to update table in order
 Simplifies commit:
 Record that mapping between architectural register and physical register
is no longer speculative
 Free up physical register used to hold older value
 In other words: SWAP physical registers on commit
 Physical register de-allocation is more difficult

Copyright © 2012, Elsevier Inc. All rights reserved. 12


Adv. Techniques for Instruction Delivery and Speculation
Integrated Issue and Renaming
 Combining instruction issue with register
renaming:
 Issue logic pre-reserves enough physical
registers for the bundle (fixed number?)
 Issue logic finds dependencies within
bundle, maps registers as necessary
 Issue logic finds dependencies between
current bundle and already in-flight bundles,
maps registers as necessary

Copyright © 2012, Elsevier Inc. All rights reserved. 13


Adv. Techniques for Instruction Delivery and Speculation
How Much?
 How much to speculate
 Mis-speculation degrades performance and
power relative to no speculation
 May cause additional misses (cache, TLB)
 Prevent speculative code from causing
higher costing misses (e.g. L2)

 Speculating through multiple branches


 Complicates speculation recovery
 No processor can resolve multiple branches
per cycle
Copyright © 2012, Elsevier Inc. All rights reserved. 14
Adv. Techniques for Instruction Delivery and Speculation
Energy Efficiency
 Speculation and energy efficiency
 Note: speculation is only energy efficient
when it significantly improves performance

 Value prediction
 Uses:
 Loads that load from a constant pool
 Instruction that produces a value from a small set
of values
 Not been incorporated into modern
processors
 Similar idea--address aliasing
Copyright © 2012, Elsevier Inc. prediction--is
All rights reserved. 15

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