L5 DLD Boolean Simplification
L5 DLD Boolean Simplification
Faculty:
Shaista Ashraf
Computer Sciences Department,
Bahria University (Karachi Campus)
Summary
Boolean Addition
In Boolean algebra, a variable is a symbol used to represent
an action, a condition, or data. A single variable can only
have a value of 1 or 0.
The complement represents the inverse of a variable and is indicated
with an overbar. Thus, the complement of A is A.
A literal is a variable or its complement.
Addition is equivalent to the OR operation. The sum term is 1 if one or
more if the literals are 1. The sum term is zero only if each literal is 0.
Determine the values of A, B, and C that make the sum term
of the expression A + B + C = 0?
1. A + 0 = A 7. A . A = A
2. A + 1 = 1 8. A . A = 0
=
3. A . 0 = 0 9. A = A
4. A . 1 = A 10. A + AB = A
5. A + A = A 11. A + AB = A + B
6. A + A = 1 12. (A + B)(A + C) = A + BC
Summary
Rules of Boolean Algebra
Rules of Boolean algebra can be illustrated with Venn
diagrams. The variable A is shown as an area.
The rule A + AB = A can be illustrated easily with a diagram. Add
an overlapping area to represent the variable B.
The overlap region between A and B represents AB.
A B A
AB =
This
Thistime,
time,AAisisrepresented
representedby bythe
theblue
bluearea
areaand
andBB
again
againby
bythe
thered circle. The intersection represents
redcircle.
AB. Notice that A + AB = A + B
A
A BA
AB
Summary
Rules of Boolean Algebra
Rule 12, which states that (A + B)(A + C) = A + BC, can
be proven by applying earlier rules as follows:
(A + B)(A + C) = AA + AC + AB + BC
= A + AC + AB + BC
= A(1 + C + B) + BC
= A . 1 + BC
= A + BC
A B A B
A+B
A+C = BC
C C
(A + B)(A + C) A + BC
Summary
DeMorgan’s Theorem
DeMorgan’s 1st Theorem
The complement of a product of variables is
equal to the sum of the complemented variables.
AB = A + B
Applying DeMorgan’s first theorem to gates:
A A Inputs Output
AB A+B
B B
A B AB A + B
NAND Negative-OR 0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0
Summary
DeMorgan’s Theorem
DeMorgan’s 2nd Theorem
The complement of a sum of variables is equal to
the product of the complemented variables.
A+B=A.B
Applying DeMorgan’s second theorem to gates:
A A Inputs Output
A+B AB
B B
A B A + B AB
NOR Negative-AND 0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0
Summary
DeMorgan’s Theorem
AB
The cells are ABC and ABC. AB ABC ABC
AB
AB ABC ABC
ABC
Summary
Karnaugh maps
K-maps can simplify combinational logic by grouping
cells and eliminating variables that change.
Group the 1’s on the map and read the minimum logic.
CC 00 11
AAB
B
11 1. Group the 1’s into two overlapping
00
00
B changes groups as indicated.
across this 01
01 11 11 2. Read each group by eliminating any
boundary variable that changes across a
11
boundary.
10
10 C changes 3. The vertical group is read AC.
across this 4. The horizontal group is read AB.
boundary
X = AC +AB
Summary
Karnaugh maps
A 4-variable map has an adjacent cell on each of its four
boundaries as shown.
Each cell is different only by
CD CD CD CD
one variable from an adjacent
AB
cell.
AB Grouping follows the rules
AB
given in the text.
The following slide shows an
AB
example of reading a four
variable map using binary
numbers for the variables…
Summary
Karnaugh maps
Group the 1’s on the map and read the minimum logic.
C changes across
outer boundary
CD
AB
00 01 11 10 1. Group the 1’s into two separate
00 1 1 groups as indicated.
B changes 2. Read each group by eliminating
01 1 1 any variable that changes across a
11 1 1
boundary.
B changes 3. The upper (yellow) group is read as
10 1 1 AD.
C changes
4. The lower (green) group is read
as AD.
X
X = AD +AD
Summary
Hardware Description Languages (HDLs)
A Hardware Description Language (HDL) is a tool for
implementing a logic design in a PLD. One important
language is called VHDL. In VHDL, there are three
approaches to describing logic:
1. Structural Description is like a schematic
(components and block diagrams).
2. Dataflow Description
Description is
is equations,
equations, such
such as
as
Boolean
Boolean operations,
operations, and
and registers.
registers.
3. Behavioral Description
Description is
is specifications
specifications over
over
time
time (state
(state machines,
machines, etc.).
etc.).
Summary
Hardware Description Languages (HDLs)
The data flow method for VHDL uses Boolean-type statements. There
are two-parts to a basic data flow program: the entity and the
architecture. The entity portion describes the I/O. The architecture
portion describes the logic. The following example is a VHDL program
showing the two parts. The program is used to detect an invalid BCD
code.
entity BCDInv is
port (B,C,D: in bit; X: out bit);
end entity BCDInv
architecture Invalid of BCDInv
begin
X <= (B or C) and D;
end architecture Invalid;
Summary
Hardware Description Languages (HDLs)
Another standard HDL is Verilog. In Verilog, the I/O and the logic is
described in one unit called a module. Verilog uses specific symbols to
stand for the Boolean logical operators.
The following is the same program as in the previous slide, written
for Verilog: