1

Arithmetic for Computer

 2

Positive Binary Numbers

 3

Negative Numbers
 4

2’s Complement
 5

Signed Operations
 6

Signed Extension
 7

Binary Subtraction
 8

Arithmetic Logic Unit (ALU)

 9

N-bit ALU
 Logic operations

Sometimes operations on individual bits needed:

Logic operation C operation MIPS instruction

Shift left logical << sll
Shift right logical >> srl
Bit-by-bit AND & and, andi
Bit-by-bit OR | or, ori


and and andi can be used to turn off some bits;
or and ori turn on certain bits

Of course, AND en OR can be used for logic operations.
 Note: Language C’s logical AND (&&) and OR (||) are conditional

andi and ori perform no sign extension !

TU/e Processor Design 5Z032 10

An ALU (arithmetic logic unit)

Let's build an ALU to support the andi and ori
instructions
 we'll just build a 1 bit ALU, and use 32 of them

operation

a result
b

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Review: The Multiplexor

Selects one of the inputs to be the output, based on a
control input
S note: we call this a 2-input mux
even though it has 3 inputs!

A 0
C
B 1


Lets build our ALU and use a MUX to select the
outcome for the chosen operation

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Different Implementations

Not easy to decide the “best” way to build something
 Don't want too many inputs to a single gate
 Don’t want to have to go through too many gates
 For our purposes, ease of comprehension is important

Let's look at a 1-bit ALU for addition (= full-adder):
CarryIn
cout = a b + a cin + b cin
a sum = a xor b xor cin
+ Sum
b

CarryOut

How could we build a 1-bit ALU for add, and, and or?

How could we build a 32-bit ALU?
TU/e Processor Design 5Z032 13
 Building a 32 bit ALU CarryIn Operation

a0 CarryIn
Operation ALU0
Result0
b0
CarryIn CarryOut

a a1 CarryIn
0 ALU1
Result1
b1
CarryOut

1
Result
a2 CarryIn
Result2
ALU2
b2
2 CarryOut
b

CarryOut
a31 CarryIn
Result31
ALU31
b31

TU/e Processor Design 5Z032 14

What about subtraction (a – b) ?

Two's complement approach: just negate b and add

How do we negate?
Binvert Operation

A very clever solution: CarryIn

a
0

1
Result

b 0 2

CarryOut

TU/e Processor Design 5Z032 15

Tailoring the ALU to the MIPS

Need to support the set-on-less-than instruction (slt)
 remember: slt rd,rs,rt is an arithmetic instruction
 produces a 1 if rs < rt and 0 otherwise
 use subtraction: (a-b) < 0 implies a < b


Need to support test for equality
 beq $t5, $t6, label
 jump to label if $t5 = $t6
 use subtraction: (a-b) = 0 implies a = b

TU/e Processor Design 5Z032 16

 Binvert Operation

Supporting 'slt'
CarryIn

a
0


Can we figure out the Result

idea? b 0 2

1
(fig. 4.17 2nd ed.)
Less 3

bits 0-30
a. CarryOut

Binvert Operation
CarryIn

a
0

Result
b 0 2

Less 3

Set

bit 31 Overflow
Overflow
detection
b.
Overflow in two’s complement
addition
° Definition: When two values of the same signs are
added:
• Result won’t fit in the number of bits provided
• Result has the opposite sign.

Overflow?
CN
CN-1

Assumes an N-bit adder, with bit N-1 the MSB

 Addition cases and overflow

00 01 11 10 00 11
0010 0011 1110 1101 0010 1110
0011 0110 1101 1010 1100 0100
-------- -------- -------- -------- -------- --------
0101 1001 1011 0111 1110 0010
2 3 -2 -3 2 -2
3 6 -3 -6 -4 4
5 -7 -5 7 -2 2
OFL OFL
Supporting Binvert CarryIn Operation

the ‘slt’ a0
b0
CarryIn
ALU0 Result0

operation Less
CarryOut

a1 CarryIn
b1 ALU1 Result1
0 Less
CarryOut

a2 CarryIn
b2 ALU2 Result2
0 Less
CarryOut

CarryIn

a31 CarryIn Result31

b31 ALU31 Set
0 Less Overflow

TU/e Processor Design 5Z032 20

 Test for equality Bnegate Operation


a-b = 0 a=b a0
b0
CarryIn
ALU0
Result0
Less

Notice control lines: CarryOut

000 = and a1
b1
CarryIn
ALU1
Result1

001 = or 0 Less
Zero
CarryOut
010 = add
110 = subtract
a2 CarryIn
111 = slt b2 ALU2
Result2
0 Less
CarryOut

• Note: signal Zero is a 1 when the

result is zero!
• The Zero output is always calculated a31 CarryIn
Result31
b31 ALU31 Set
0 Less Overflow

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ALU symbol
operation

32
a
zero
32
ALU result
overflow
32
b

carry-out

TU/e Processor Design 5Z032 22

 Conclusions

We can build an ALU to support the MIPS instruction set
 key idea: use multiplexor to select the output we want
 we can efficiently perform subtraction using two’s complement
 we can replicate a 1-bit ALU to produce a 32-bit ALU

Important points about hardware
 all of the gates are always working
 not efficient from energy perspective !!
 the speed of a gate is affected by the number of connected
outputs it has to drive (so-called Fan-Out)
 the speed of a circuit is affected by the number of gates in series
(on the “critical path” or the “deepest level of logic”)
 Unit of measure: FO4 = inverter with Fan-Out of 4
 P4 (heavily superpipelined) has about 15 FO4 critical path

TU/e Processor Design 5Z032 23

Multiplication (0)

More complicated than addition
 accomplished via shifting and addition

More time and more area

Let's look at 3 versions based on grade school
algorithm

0010 (multiplicand)
__*_1011 (multiplier)


Negative numbers: convert and multiply
 there are better techniques, we will look at them later

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Multiplication (1)
Start

First implementation
Product initialized to 0 Multiplier0 = 1 1. Test Multiplier0 = 0
Multiplier0

Multiplicand 1a. Add multiplicand to product and

Shift left place the result in Product register

64 bits

Multiplier 2. Shift the Multiplicand register left 1 bit

64-bit ALU Shift right
32 bits
3. Shift the Multiplier register right 1 bit
Product
Control test
Write
64 bits
No: < 32 repetitions
32nd repetition?

Yes: 32 repetitions

Done

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Multiplication (2) Start

Second version Multiplier0 = 1 1. Test

Multiplier0
Multiplier0 = 0

1a. Add multiplicand to the left half of

the product and place the result in
the left half of the Product register
Multiplicand

32 bits
2. Shift the Product register right 1 bit

Multiplier
32-bit ALU Shift right
3. Shift the Multiplier register right 1 bit
32 bits

Shift right
Product Control test No: < 32 repetitions
Write 32nd repetition?

64 bits
Yes: 32 repetitions

Done

TU/e Processor Design 5Z032 26

Multiplication (3)
Start

Final version
Product initialized with multiplier Product0 = 1 1. Test Product0 = 0
Product0

Multiplicand
1a. Add multiplicand to the left half of
the product and place the result in
32 bits the left half of the Product register

32-bit ALU
2. Shift the Product register right 1 bit

Shift right Control

Product
Write test
No: < 32 repetitions
64 bits 32nd repetition?

Yes: 32 repetitions

Done

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Example 1
Use the Final version of multiplication algorithm to find 9 x 12 = 108 multiplier
12 and multiplicand 9

TU/e Processor Design 5Z032 28

Example 2 Alg. 3
2 * 3 =? Mcand =2 Mtlier = 3 each size is 4 bits

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Division (1)

Similar to multiplication: repeated subtract

The book discusses again three versions

We will look at one version

We have divisor( 32) , dividend(64) and quotient (32)

Three registers: The divisor and remainder 64 bits
quotient 32 bits

Initially divisor is placed in left half of divisor reg and
dividend is placed in remainder registers.

Do steps in next slide and repeat 33 times divisor +1

There are other two algorithms see the

book for more details.
TU/e Processor Design 5Z032 30
 Start

Division (2)
1. Substract the Divisor register from the
Remainder register and place the
result in the Remainder register

Implementation:

Repeat 33 times >= 0
Test Remainder
<0

Divisor is placed in left
half of divisor register
2.a Shift the Quotient register 2.b Restore the original value by
to the left, setting the adding the Divisor register. Also,
rightmost bit to 1 shift a 0 into the Quotient register

Divisor
Shift right Shift Divisor Register right 1 bit
64 bits

Quotient no
64-bit ALU
Shift left 33rd repetition?
32 bits

Remainder Control test

yes
Write
64 bits
Done

TU/e Processor Design 5Z032 31

TU/e Processor Design 5Z032 32
Division example

33
Modified Booth Recoding algorithm

Booth's algorithm is a multiplication algorithm that
multiplies two signed binary numbers in 2's
compliment notation.


One advantage of the Booth multiplier is, it reduce
the number of partial product. The number of steps is
reduced in Half. Can do 8 bit multiplication in 4 steps.


The main disadvantage of Booth multiplier is the
complexity of the circuit to generate a partial product
bit in the Booth encoding.

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 How do we recode the multipiler

Add 0 the right of the multiplier and starting form right group the multiplier
into three bit groups and generate a code according to the following table.
The last bit in one group will also be the frst bit in the next group. See
examples below

Example if multiplier is 9 and assume 5 bits then value is 01001 -> insert 0
right value becomes 0010010 then recoding groups from right are :
010 (1)
100 (-2) and 001 (1). You can insert as many 0 bits to left to the last group
the make it three bits.
If multiplier is -9 and assume 5 bits then value is 10111 -> insert 0 right
value 1101110 then recoding groups from right: 110 ( -1), 011 (2) and 110 (-1)
You can insert as many 1 to left as needed to the last group to make three 35
 Modified Booth Recoding algorithm example
Assume we want to find 7 x -9. assume 5 bits are used then
7 in binary 0011 and -9 from recoding see last slide is -1, 2, -1 to find
the final product we add the following partial products:
-1 x 7 shifted 0 bits to the left,
2 x 7 shifted left 2 bits
-1 x 7 shifted left 4 bits.

TU/e Processor Design 5Z032 36

Booth Recoding algorithm; example 2
find 14 x 21 assume 21 multiplier we need 6 bits to represent multiplier 21
signed representation. 21: 010101 three groups
Insert 0 right the groups become 010 (1) 010 (1) 010 (1)
Then we need partial products 01110 shifted 0, 2 and 4 respectively as seen
below then add the partial products to get the final value 14 X 21 = 294
More examples found in https://www.youtube.com/watch?v=SGnab30ISwg
https://www.youtube.com/watch?v=FMMHJlLduU

more examples found: https://www.youtube.com/watch?v=SGnab30ISwg

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Another example 6 * 6
0110 ‐ multiplicand as base 2 = +6
0110 – multiplier as base 2 = +6
Mutiplier recodeing 01100 groups (011) and (100)
+2 ‐2 – multiplier recoded with Booth’s
product = +2*4 *6 + (‐2) *6
= 111110100 – first partial product = ‐2*(+6) <<0

+ 000110000 ‐ second partial product = +2*(+6)<<2

000100100 – final product = +36
Try - 6 * - 6 get same answer

TU/e Processor Design 5Z032 38

Another example -6 * 6
1010 ‐ multiplicand as base 2 = -6
1100 – multiplier as base 2 = +6
Mutiplier recodeing 01100 groups (011) and (100)
+2 ‐2 – multiplier recoded with Booth’s
product = +2*4 *-6 + (‐2) *-6
= 00001100 – first partial product = ‐2*(- 6) <<0

+ 11010000 ‐ second partial product = +2*(+6)<<2

11011100 – final product = -36

TU/e Processor Design 5Z032 39

Summary

Booth recoding add zero right of multiplier group 3 bits
and find recoding overlap last bit of a group as the
first bit next group.

For each recoding value multiply value with
multiplicand and shift result by b bits. 0,2,4..

Add partial products.

Steps half of multiple before

And signed multiplication

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