8086 Hardware Specifications

Course Teacher:
Deboky Saha (DES)
Contractual Lecturer
Dept. of Computer Science and Engineering
BRAC University
CSE 341
8086 Pin Specification
 8086 is packaged as 40-pin DIPs.
 In micro-electronics DIP stands for Dual in-line package.
 DIP packaging refers to a rectangular housing with two parallel
rows of electrical connection pins.
 DIP chips have a notch on one end to show its correct
orientation.
 The pins are then numbered as shown in the figure below.

2
8086 Pin Specification

3
Power Supply

Vcc
Vcc

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

GND GND
GND GND

4
Multiplexed Data and Address Bus
Multiplexed AD0 – AD15 A16 – A19 BHE / S7
Signals Or Or
D0 – D15 S3 – S6
When ALE =1 AD0 – AD15 A16 – A19 BHE

When ALE =0 D0 – D15 S3 – S6 S7

Multiplexing helps in reducing the number of pins by combining signals. If these

pins were not multiplexed they would have consumed 42 pins of uP. Due to
multiplexing 42 pins has been reduced to 21 pins. Thus, the number of pins has
been reduced tremendously.

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Pins for Data and Address Bus
 Data Bus (AD0 – AD15)
 These 16 pins form the CPU’s bidirectional data bus

 Address Bus (AD0 – AD15 and A16/S3 – A19/S6)

 These 20 pins correspond to the CPU’s 20-bit address bus
and allow the processor to access 220 or 10, 48, 576 unique
memory locations.

 Address Latch Enable (ALE) (Pin 25)

 Line carries address when ALE =1
 Line carries data when ALE =0

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Control Signal – BHE
 The Bus High Enable (BHE) pin is used in the 8086 to
enable the Most significant data bus bits during a read or
write operation. It helps in the selection of higher bank or
odd bank in memory banking.
AD15 BHE/S7
READY
Vcc A16/S3 …A19/S6 RD TEST RESET

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

GND NMI GND

INTR
CLK
7
Control Signal –Segment Register Status
 This information indicates which segment register is presently
being used for data accessing.

S4 S3 Function
0 0 ES
0 1 SS
1 0 CS or no segment
1 1 DS

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Status Signals
 S5: Indicates if interrupt is enabled or disabled.
If S5 =1 , then the IF = 1, so the interrupt is enabled.
If S5 =0 , then the IF = 0, so the interrupt is disabled.

 S6 : Indicates if 8086 is the bus master or not

If S6 = 0 , 8086 is the bus master
If S6 = 1 , 8086 is not the bus master

 S7 : Reserved for further development

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Pins for Data and Address Bus

AD15

A16/S3 … A19/S6

Vcc

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

GND GND
AD14 ……… AD0
10
Control Signal –
Minimum and Maximum Mode
 The mode is selected by PIN 33
 1 = Minimum, 0 = Maximum
 Use of Pin 24 to 31 changes with the mode.

 The minimum mode is intended for single-processor

systems on one printed circuit board (PCB).

 The maximum mode is intended for more complex

system with separate I/O and memory boards.

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Control Signal –
Minimum and Maximum Mode
MN/MX
BHE/S7

MN/MX
AD15 READY
Vcc A16/S3 …A19/S6 RD RESET
TEST

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

GND AD0 .................................................................... AD14 NMI GND

CLK
12
INTR
Control Signal – Clock
 Clock provides the basic timing for the processor and bus
controller.
 It is asymmetric with a 33% duty cycle to provide optimized
internal timing.
 8086 is found to operate in 5 and 10 Mhz.
AD15
Vcc A16/S3 …A19/S6

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

GND AD0 .................................................................... AD14 NMI

INTR GND
13
CLK
Control Signal – Interrupts
 INTR: Interrupt request pin is used to request a hardware
interrupt. It is a lower priority interrupt and non-vectored.
 If INTR is held at high when Interrupt Flag (IF=1), the
processor goes into the interrupt acknowledgement cycle.
INTA becomes active when interrupt is being serviced and it
sends vector number to INTR.
AD15
Vcc A16/S3 …A19/S6

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

GND AD0 .................................................................... AD14 NMI GND

14
INTR
CLK
Control Signal – Interrupts
 NMI: Non-maskable interrupt input is similar to INTR
expect that the NMI interrupt does not check Interrupt Flag
(IF) or priority. Acknowledgment is not needed here as it is
vectored.
AD15
Vcc A16/S3 …A19/S6

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

GND AD0 .................................................................... AD14 INTR GND

CLK
NMI
15
Control Signal – RESET
 RESET If this reset pin is held high for 4 clock cycles the
microprocessor resets. As soon as power is applied to
8086, reset pin is activated.
AD15 RESET
Vcc A16/S3 …A19/S6
RESET
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

GND AD0 .................................................................... AD14 NMI GND

INTR
CLK

16
Control Signal – READ
 RD: When this read signal pin is at logic 0, the data bus
is receptive to data from memory or I/O devices.

AD15 RD
READY
Vcc A16/S3 …A19/S6 TEST RESET

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

GND NMI GND

INTR
CLK

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Control Signals – Minimum Mode
 INTA (Pin 24): Interrupt acknowledgement signals is a
response to INTR input pin. This is used when the
interrupt vector is placed on the address bus by the
microprocessor.
 ALE (Pin 25): Address Latch enable shows whether
the multiplexed AD lines carry address or data.
 DEN (Pin 26): Data Enable bus activates external data
bus buffers.
 DT/R (Pin 27): Data transmit/receive shows that the
microprocessor data bus is transmitting(1) or receiving(0)
data. This is used to control buffers.
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Control Signals – Minimum Mode
 M/IO (Pin 28): This pin indicates whether the address
bus contains a memory address or an I/O port address.
 WR (Pin 29): The write line is a used when the
microprocessor is writing data to memory and the memory
bus contains a valid address.
 HOLD (Pin 30): HOLD pin is used to input request
DMA (Direct Memory Access). Hold set to 1
microprocessor gives up control of buses to DMA
controller.
 HLDA (Pin 31): HLDA pin is used to acknowledge DMA
request.
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Control Signal – READY
 The READY pin is used to enforce a waiting state.
 READY pin at 0 – the microprocessor goes into idle state.
READY pin at 1 – the microprocessor does normal operation.

AD15
Vcc
READY
A16/S3 …A19/S6 RESET

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

NMI
GND AD0 .................................................................... AD14 INTR GND
CLK

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READY
 uP samples the READY input during T3 state of every
machine cycle (or bus cycle).
 If devices are not ready, the READY signal becomes 0. In
that case uP will enter into “wait state”
 “Wait states” are basically empty clock cycle between T3
and T4 states of machine cycle.
 It simply means uP is allowing the slower devices more
time to get ready and complete the operation.
 As long as the READY signal is 0, the uP remains in wait
state and once it becomes 1, uP comes out of “wait state”
and continue with the normal operation

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Control Signal – TEST
 TEST: Test pin is an input that is tested by the WAIT instruction.
 If the test pin is at logic 0 the WAIT instruction functions as NOP
(No operation). It means there is no “wait state” . If test is a logic 1,
the WAIT instruction wait for TEST to become logic 0. It is most
often connected with 8087 processor in MAX mode

AD15
TEST READY
Vcc A16/S3 …A19/S6 RESET

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

GND NMI GND

22 INTR
CLK
Remember !! 8086 Pin Specifications

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Microprocessor Operation

Fetch Decode

Execute

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Microprocessor Operation
 The time a µP requires to complete fetch-decode-execute
operation of a single instruction is known as Instruction
Cycle
 An Instruction Cycle consists of one or more Machine
Cycles
 A basic µP operation such as reading or writing a byte
from or to memory or I/O port is called a Machine Cycle
or Bus cycle
 A Machine (bus) cycle consists of at least four clock
cycles, called T states.
 One cycle of a clock is called a State

25
Clock Generation
 Clock generator circuit is 8284A and connected to pin 19
(CLK) of 8086.

26
System Clock Concept

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System Clock Concept
 8086 is found to operate in between 5 to 10 Mhz.
 Each bus cycle consists of 4 clock cycles.
 An 8086 running at 5MHz, it’s clock pulses will be of
200ns and it would take 800ns for a complete bus cycle.
 Again, an 8086 running at 10MHz, it’s clock pulses will
be of 100ns and it would take 400ns for a complete bus
cycle.
 Each read or write operation take 1 bus cycles.

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Clock States
 Why are there T states?
 In the 8086, the address and data lines are
multiplexed.
 The microprocessor needs time to change the
signals during each bus cycle.
 Memory devices need time to interpret the address
value and then read/write the data (access time)

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Clock States
 A specific, defined action occurs during each T states
(labeled T1 – T4)

 T1: Address is output

 Address of memory is sent out by 8086 via address bus
 Used Control signals: ALE, DT/R’, M/IO’ shows some
output

 T2: Bus cycle type (MEMORY/IO, READ/WRITE)

 8086 issues either RD’ or WR’ and DEN’
 In case of WRITE (WR) operation, data to be written
appear on data bus
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Clock States
 T3: Data is supplied
 READY is sampled at the end of T2
 If READY is low, T3 becomes a wait state (TW), means no
operation (NOP).
 In READ bus cycle data bus is sampled at end of T 3

 T4: Data latched by µP, control signals removed

 All bus signals deactivated in preparation for next bus cycle
 µP sampled data bus for data that read from M or I/O
 At trailing edge of WR’, transfer data to M or I/O

31
READ BUS Timing (Complete BUS Cycle)

32
WRITE BUS Timing

 What are the functions of each pin in different T states

during WRITE operation ??
33
Ready pin and Wait state

The READY input causes wait states for slower memory

and I/O components. A wait state is a situation in which a
computer processor is waiting for the completion of some
event before resuming activity. A program or process in a
wait state is inactive for the duration of the wait state. In
general, the more time a processor spends in wait states, the
slower the performance of that processor. Wait states are a
pure waste for a processor's performance. Modern designs
try to eliminate or hide them using a variety of techniques.

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 Thank You !!

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