CHAPTER 5

- Dr. T.KAVITHA,
ASSOC.PROF.
MVSREC
 COMPLEX INSTRUCTION SET COMPUTERS: CISC

High Performance General Purpose Instructions

Characteristics of CISC:
1. A large number of instructions (from 100-250 usually)
2. Some instructions that performs a certain tasks are not
used frequently.
3. Many addressing modes are used (5 to 20)
4. Variable length instruction format.
5. Instructions that manipulate operands in memory.
 CHARACTERISTICS OF RISC

- Relatively few instructions

- Relatively few addressing modes
- Memory access limited to load and store instructions
- All operations done within the registers of the CPU
- Fixed-length, easily decoded instruction format
- Single-cycle instruction format
-Hardwired rather than micro programmed control
-A relatively large numbers of registers in the processor unit.
-Efficient instruction pipeline
- efficient Compiler support
PIPELINING AND VECTOR PROCESSING

• Parallel Processing

• Pipelining

• Arithmetic Pipeline

• Instruction Pipeline

•VLIW processor
 Parallel Processing

PARALLEL PROCESSING
Parallel processing is a term used to denote a large class of techniques that are
used to provide simultaneous data-processing tasks for the purpose of
increasing Computational speed of a computer system.

Instead of processing each instruction sequentially ,a parallel processing

system is able To perform concurrent data processing.

It can be achieved by two or more functional units (ALU’s).The amount of

hardware increases and the cost of the system too, but because of
Technological developments, It is feasible.

Execution of Concurrent Events in the computing

process to achieve faster Computational Speed or increase throughput

- Program level

- Task level
Levels of Parallel Processing
- Instruction level

- DATA level
 Parallel Processing

PARALLEL COMPUTERS
– Flynn's classification
Based on the number of Instruction Streams and Data Streams that are
manipulated simultaneously

• Instruction Stream
– Sequence of Instructions read from memory
• Data Stream
– Operations performed on the data in the processor

Number of Data Streams

Single Multiple

Number of Single SISD SIMD

Instruction
Streams Multiple MISD MIMD
 Parallel Processing

SISD COMPUTER SYSTEMS

Control Processor Data stream

Memory
Unit Unit

Instruction stream

Characteristics
- Standard von Neumann machine
- Instructions and data are stored in memory
- One operation at a time

Instructions are executed sequentially and the system may or may not have
parallel processing capabilities.

Von Neumann bottleneck

- Limitation on Memory Bandwidth

- Memory is shared by CPU and I/O
 Parallel Processing

MISD COMPUTER SYSTEMS

M CU P

M CU P Memory
• •
• •
• •

M CU P Data stream

Instruction stream

Characteristics
- There is no computer at present that can be
classified as MISD
 Parallel Processing

SIMD COMPUTER SYSTEMS

Memory
Data bus

Control Unit
Instruction stream
Characteristics

Many processing units

under the supervision of one P P ••• P Processor units
control unit but operates on
different type of data. Data stream

The shared memory unit must Alignment network

contain multiple modules so that
It can communicate with all the
Processors simultaneously.
M M ••• M Memory modules
 Parallel Processing

MIMD COMPUTER SYSTEMS

P M P M ••• P M

Interconnection Network

Shared Memory

Characteristics
- Multiple processing units

- Execution of multiple instructions on multiple data

Capable of processing several programs at the same time. Most multi-

processor and multi computer systems can be classified under this category.
 Applications of Parallel Processing
• Numerical weather forecasting
• Aerodynamics
• Finite element analysis
• Remote sensing applications
• Genetic engineering
• Computer assisted Tomography
• Weapon research
• Defence
• Parallel processing is discussed under

– Pipeline processing
– Vector processing
– Array processors
 PIPELINING

A technique of decomposing a sequential process into

sub operations, with each sub process being executed in
a partial dedicated segment that operates concurrently
with all other segments.

1.Arithmetic Pipeline
2.Instruction Pieline
 Pipelining

GENERAL PIPELINE
General Structure of a 4-Segment Pipeline
Clock

Input S1 R1 S2 R2 S3 R3 S4 R4

Space-Time Diagram
1 2 3 4 5 6 7 8 9 Clock cycles
Segment 1 T1 T2 T3 T4 T5 T6
2 T1 T2 T3 T4 T5 T6
3 T1 T2 T3 T4 T5 T6
4 T1 T2 T3 T4 T5 T6
 Pipelining

PIPELINE SPEEDUP
n: Number of tasks to be performed

Conventional Machine (Non-Pipelined)

tn: Clock cycle
: Time required to complete the n tasks
 = n * t n

Pipelined Machine (k stages)

tp: Clock cycle (time to complete each suboperation)
: Time required to complete the n tasks
 = (k + n - 1) * tp The first task T1 req. a time equal to ktp to complete
its operation since there are k-segments in the pipe.

Speedup The remaining (n-1) tasks emerge from the pipe at the rate of
one task per clock cycle and will be completed in (n-1)tp.
Sk: Speedup

Sk = n*tn / (k + n - 1)*tp If ‘n’ becomes larger than K-1 and K+n-1 approaches
The value of ‘n’.
tn
lim Sk = ( = k, if tn = k * tp )
n tp
 Pipelining

PIPELINE AND MULTIPLE FUNCTION UNITS

Example
- 4-stage pipeline
- subopertion in each stage; tp = 20nS
- 100 tasks to be executed
- 1 task in non-pipelined system; 20*4 = 80nS

Pipelined System
(k + n - 1)*tp = (4 + 99) * 20 = 2060nS

Non-Pipelined System
n*k*tp = 100 * 80 = 8000nS

Speedup
Sk = 8000 / 2060 = 3.88

4-Stage Pipeline is basically identical to the system

Ii Ii+1 I i+2 I i+3
with 4 identical function units

Multiple Functional Units P1 P2 P3 P4

 ARITHMETIC PIPELINE
Floating-point adder Exponents
a b
Mantissas
A B

R R
X=Ax2 a

Y = B x 2b Compare Difference
Segment 1: exponents
by subtraction
4-Segments and their function
R
[1] Compare the exponents
[2] Align the mantissa Segment 2: Choose exponent Align mantissa
[3] Add/sub the mantissa
[4] Normalize the result R

Segment 3: Add or subtract

mantissas

R R

Segment 4: Adjust Normalize

exponent result

R R
 X=0.95404x103
Y=0.8200x102

1.The two exponents are subtracted in the first segment.

2. The larger exponent is chosen as the exponent of the

result.

3. The next segment shifts the mantissa of Y to the right to

obtain =0.0820x103

4. This aligns the two mantissas under the Same exponent.

5. Addition of two mantissas in segment 3 produces the

sum.

Z =1.0234x103;

6.Normalize the result; Z =0.10234x104

 Instruction Pipeline

INSTRUCTION CYCLE pipeline

Instruction Pipeline: Pipeline processing can occur not only in the data
stream but in the instruction stream as well.

An instruction pipeline reads consecutive instructions from memory while

previous instructions are being executed in other segments.

This cause the instructions fetch and execute phases to overlap and
perform simultaneous operations.
 INSTRUCTION CYCLE
Six Phases* in an Instruction Cycle

[1] Fetch an instruction from memory

[2] Decode the instruction
[3] Calculate the effective address of the operand
[4] Fetch the operands from memory
[5] Execute the operation
[6] Store the result in the proper place

* Some instructions skip some phases

* Effective address calculation can be done in
the part of the decoding phase
* Storage of the operation result into a register
is done automatically in the execution phase
==> 4-Stage Instruction Pipeline

[1] FI: Fetch an instruction from memory

[2] DA: Decode the instruction and calculate
the effective address of the operand
[3] FO: Fetch the operand
[4] EX: Execute the operation
 Instruction Pipeline

INSTRUCTION PIPELINE
Execution of Three Instructions in a 4-Stage Pipeline

Conventional

i FI DA FO EX

i+1 FI DA FO EX

i+2 FI DA FO EX

Pipelined

i FI DA FO EX
i+1 FI DA FO EX
i+2 FI DA FO EX
 Instruction Pipeline

INSTRUCTION EXECUTION IN A 4-STAGE PIPELINE

Segment1: Fetch instruction

from memory

Decode instruction
Segment2: and calculate
effective address

yes Branch?
no
Segment3: Fetch operand
from memory

Segment4: Execute instruction

Interrupt yes
Interrupt?
handling
no
Update PC

Empty pipe
 Step: 1 2 3 4 5 6 7 8 9 10 11 12 13

Instruction 1 FI DA FO EX

2 FI DA FO EX

(Branch) 3 FI DA FO EX

4 FI FI DA FO EX

5 FI DA FO EX

6 FI DA FO EX

7 FI DA FO EX
 Pipeline conflicts or HAzards

Hazards in pipelines may make it Pipeline Interlock:

necessary to stall the pipeline Detect Hazards Stall until it is cleared
1. Structural Hazards(Resource conflicts)
caused by access to memory by two segments at the same time. With one memory,
a data and an instruction fetch cannot be initiated in the same clock

Most of these conflicts can be resolved by using separate instruction and data
memories.

i FI DA FO EX

i+1 FI DA FO EX

i+2 stall stall FI DA FO EX

Solution : The Pipeline is stalled for resource conflict Two Loads with
one port memory

-> Two-port memory will serve without stall

 2. DATA HAZARDS Data Dependency Conflicts)
Occurs when the execution of an instruction depends on the results of a
previous instruction
ADD R1, R2, R3
SUB R4, R1, R5
Data hazard can be dealt with either hardware techniques or
software technique

Hardware Technique

Interlock
- hardware detects the data dependencies and delays the scheduling
of the dependent instruction by stalling enough clock cycles.

Forwarding (bypassing, short-circuiting)

- Accomplished by a data path that routes a value from a source
(usually an ALU) to a user, bypassing a designated register. This
allows the value to be produced to be used at an earlier stage in the
pipeline than would otherwise be possible
 Cont……
Software Technique (DELAYed LOAD)
• The compiler is designed to detect a data
conflict and reorder instructions
• As necessary to delay the loading of the
conflicting data by inserting no-operation
instructions.This method is called DELAY LOAD
 Instruction Pipeline

3. CONTROL HAZARDS(Branching Difficulties)

Branch Instructions : Branches and other instructions that change the PC
make the fetch of the next instruction to be delayed

- Branch target address is not known until the branch instruction is decoded.

Branch
FI DA FO EX
Instruction
Next FI DA FO EX
Instruction

Target address available

- Stall -> waste of cycle times

Dealing with Control Hazards

* Prefetch Target Instruction

* Branch Target Buffer
* Branch Prediction
* Delayed Branch
 CONTROL HAZARDS
Prefetch Target Instruction
– Fetch instructions in both streams, instruction to be executed
if branch not taken and the instruction if branch taken

– Both are saved until branch is executed. Then, select the right
instruction stream and discard the wrong stream

Branch Target Buffer (BTB; Associative Memory)

– Present in the fetch segment of the pipeline. It has entry of

the
Address of previously executed branches i.e. their Target
instruction and the next few instructions
– When fetching an branch instruction, search BTB.
– If found, fetch the instruction stream in BTB;
– If not, new stream is fetched and update BTB
Branch Prediction
– Uses additional logic to guess the outcome of the branch
condition before it is executed.
– The instruction is fetched based on the guess. Correct
guess eliminates the branch penalty

Delayed Branch

– Compiler detects the branch and rearranges the

instruction sequence by inserting useful instructions that
keep the pipeline busy in the presence of a branch
instruction
 VLIW processor
• The intrinsic parallelism in the instruction stream,
complexity, cost, and the branch instructions issue
get resolved by a higher instruction set architecture
called the Very Long Instruction Word
(VLIW) or VLIW Machines.

• VLIW uses Instruction Level Parallelism, i.e. it has

programs to control the parallel execution of the
instructions.
Features :

The processors in this architecture have multiple functional

units, fetch from the Instruction cache that have the Very Long
Instruction Word.

Multiple independent operations are grouped together in a

single VLIW Instruction. They are initialized in the same clock
cycle.

Each operation is assigned an independent functional unit. All

the functional units share a common register file.
Instruction words are typically of the length 64-1024 bits
depending on the number of execution unit and the code
length required to control each unit.

Instruction scheduling and parallel dispatch of the word is

done statically by the compiler.

The compiler checks for dependencies before scheduling

parallel execution of the instructions.