A real-world clock generator

class for UVM

Rhitam Datta, Design Engineer
Ankit Somani, Design Lead

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 Topics
• Introduction
• Importance of clocking signal in design verification: SerDes
Illustration
• Irregularities in clock
• Module based clock generator
• Proposed class based clock generator
• Generic architecture of class based clock generator
• Simulation results
• Summary
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 Introduction
• A particular type of signal that toggles between a
high state and low state, typically used to manage
various operations in digital circuits.

• A typical example is a periodic square wave with 50%

duty cycle.
Time period

Frequency

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 Introduction
• It can have duty cycle not equal to 50%.
High time

Low time

• It can have different rise time and fall time.

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Importance of clocking signal in design
verification: SerDes Illustration

parallel_data[7:0]

parallel_clk serial_data
Serializer
serial_clk

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Importance of clocking signal in design
verification: SerDes Illustration

parallel_data[7:0]

serial_data parallel_clk
DeSerializer

serial_clk

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 Importance of clocking signal in design
verification: SerDes Illustration

Exhibits low pass

characteristics
and includes
noise

par_data par_data
Channel
clk Serializer DeSerializer clk

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 Importance of clocking signal in design
verification: SerDes Illustration

par_data par_data

clk Serializer Channel DeSerializer clk

A B

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Importance of clocking signal in design
verification: SerDes Illustration
Exhibits low pass
characteristics and
includes noise

Channel
1 UI A B

Transmission of Lone 1 data stream over channel

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Importance of clocking signal in design
verification: SerDes Illustration
Exhibits low pass
characteristics and
includes noise
Analog waveform
of data

Channel
1 UI A B

Transmission of Lone 1 data stream over channel

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Importance of clocking signal in design
verification: SerDes Illustration
Exhibits low pass
characteristics and
includes noise

Channel
1 UI A B <1 UI

Transmission of Lone 1 data stream over channel

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Importance of clocking signal in design
verification: SerDes Illustration

parallel_data[7:0]

serial_data parallel_clk
DeSerializer

serial_clk

1 UI

Stimulus : Ideal datastream Ideal scenario simulation

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Importance of clocking signal in design
verification: SerDes Illustration

parallel_data[7:0]

serial_data parallel_clk
DeSerializer

serial_clk

<1 UI

Stimulus : Real datastream Real scenario simulation

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Importance of clocking signal in design
verification: SerDes Illustration

Ideal clock

Ideal Stimulus
1 UI
Non- Ideal clock

Non- Ideal Stimulus

<1UI

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Importance of clocking signal in design
verification: SerDes Illustration

Ideal clock

Non- Ideal clock

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Importance of clocking signal in design
verification: SerDes Illustration

Ideal clock

Non- Ideal clock

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 Irregularities in clock
• Causes the deviation from the periodicity of a
periodic signal, often in relation to a reference signal.
• Sourced by crystal, electromagnetic interference ,
cross talk with other signals etc.
• May effect the time period or the phase of the clock.
• Can be classified in two categories,
– Unintentional deviations are always present.
– Intentional deviations are introduced to counter certain
undesired phenomenon as EMI.

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 Irregularities in clock
• Crystal PPM error

The deviation from the nominal clock frequency,

expressed in terms of parts per million (PPM).

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 Irregularities in clock
• Wander error

Slow noise components, frequency less than 10

Hz, often are considered as Wander.

{
𝑡 𝑜𝑏𝑠= 𝑡 0 ± 𝑤𝑎𝑛𝑑𝑒𝑟 _ 𝑎𝑚𝑜𝑢𝑛𝑡 ,∧𝑐𝑙𝑜𝑐𝑘 _ 𝑐𝑦𝑐𝑙𝑒 _ 𝑛𝑜=𝑚𝑛
𝑡 0 ,∧𝑒𝑙𝑠𝑒

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 Irregularities in clock
• High probability jitter (HPJ)

Consists of various components such as duty cycle

distortion, data dependent jitter, periodic jitter etc.

Generated by passing PRBS data pattern

through a low pass filter.

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 Irregularities in clock
• Tonal jitter

Comprised of a single fundamental frequency and

prominent in the context of jitter tolerance test of RX.

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 Irregularities in clock
• Gaussian jitter

Caused by silicon imperfection, certain types of cross talk,

thermal vibration etc., can be bounded or unbounded.

where τ = x-µ

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 Irregularities in clock
• Gaussian jitter

Caused by silicon imperfection, certain types of cross talk,

thermal vibration etc., can be bounded or unbounded.

{
2
𝜏
1 −
2𝜎
2

𝐶𝐵𝐺𝐽 ( 𝑥 ) = 𝑒 ,∧¿ 𝜏 ∨¿ 𝜏 𝑚𝑎𝑥

𝜎 √2 𝜋
0 ,∧¿ 𝜏 ∨≥ 𝜏𝑚𝑎𝑥

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 Irregularities in clock
• Spread spectrum clocking

Spectrum is spread around the center frequency of

clock, to counter effect of EMI.

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Module based clock generator
Interface

DUT
(Module)

Base Test

Clock Generator
(Module)

Test Bench UVM Test case

(Module)

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Module based clock generator
Interface

DUT
(Module)

Base Test

Clock Generator
(Module)

Adding clock
control signals
Test Bench UVM Test case
(Module)

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Module based clock generator
Interface

DUT
(Module)

Base Test

Clock Generator
(Module)

Adding clock
control signals
Test Bench UVM Test case
(Module)

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Module based clock generator
Interface

DUT
(Module)

Base Test

Clock Generator
(Module)

Adding clock
control signals
Test Bench UVM Test case
(Module)

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Module based clock generator
Interface

DUT
(Module)

Base Test

Clock Generator
(Module)

Adding clock
control signals
Test Bench UVM Test case
(Module) Interface
becoming
bulkier!

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Proposed Class based clock generator

Interface

Base Test
DUT
(Module) Clock Generator
(Class)

Interface size
reduced!
Test Bench UVM Test case
(Module) Clock control
signals not
required!

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Generic architecture of class based
clock generator
class clock_gen ();
// Contents of the class clock gen
endclass : clock_gen
class uvm_base_test extends uvm_test ;
/// Other declarations
clock_gen clk_gen_h ;
function void build_phase (uvm_phase phase) ;
// Other functionalities
clk_gen_h.build () ;
endfunction : build_phase
task run_phase (uvm_phase phase);
// Other tasks
clk_gen_h.configure () ;
clk_gen_h.run () ;
endtask : run_phase
endclass : uvm_base_test

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 Simulation results
• Crystal PPM error

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 Simulation results
• Crystal PPM error

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 Simulation results
• Crystal PPM error

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 Simulation results
• Wander error

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 Simulation results
• Wander error

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 Simulation results
• Wander error

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 Simulation results
• High probability jitter

• Tonal jitter

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 Simulation results
• Gaussian jitter

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 Simulation results
• Spread spectrum clocking

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 Simulation results
• Frequency configurability

• Duty cycle configurability

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 Summary
• Clocking signals plays important role in verification.
• In test bench clocks can be generated by module
based clock generator or class based clock generator.
• In the proposed method, class based clock generator
is instantiated inside the base test of UVM.
• This gives direct control over clock generator.
• Interface becomes lighter as no clock control signals
are required.
• Class based clock generator is configurable and can
inject non-idealities in clock signals.
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 Questions ?

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