Lecture 1: Review of

Computer Organization

Operating System

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What is Operating System?
 Operating system is a program that acts
as an intermediary between a user of a
computer and the computer hardware.
 Main GOALS of an OS:
 To make the computer system convenient
to use
 To use the computer hardware in an
efficient manner
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Four Elements of a Computer
System
 Processor (CPU)
 Control the operation of the computer and its data processing
functions.
 Main Memory
 Stores data and programs
 RAM - random access memory
 I/O Modules
 Auxiliary storage like disk drives, tape drives
 Printers, terminals, monitors
 System Bus
 Provides for transfer of data among processors, main memory, and
I/O modules

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Computer Organization

CPU MAIN MEMORY

0
PC MAR 1
System
…
IR MBR Bus
Instruction
I/O AR Instruction
Execution
Instruction
Unit I/O BR
…
DATA
I/O module
DATA
buffer
… n-2
n-1

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CPU (Processors) Registers
 A processor includes a set of registers that
provide a level of memory faster than main
memory.
 User-visible Registers
 Control and Status Registers

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User-visible Registers
 Many instructions operate on data sitting on working
registers.
 Since registers are faster than main memory, it is
better that data be moved to registers before
operating on them.
 May be referenced by the machine language that the
processor executes
 available to all programs - application programs and
system programs.
 Types of registers:
 Data registers
 Address registers
 For indirect addressing
 For index register
 For segment pointer
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 For stack pointer
Control and Status Registers
 Program Controller (PC) – contains the address of an instruction
to be fetched
 Instruction Register (IR) – contains the instruction most
recently fetched
 Memory Address Register (MAR)
 Memory Buffer Register (MBR)
 I/O Address Register (I/O AR)
 I/O Buffer Register (I/O BR)
 Processor Status Word (PSW)
 condition codes or flags
 interrupt enable/disable
 user/supervisor mode

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 Instruction Cycle
Fetch Cycle Execute Cycle
Fetch next Execute
Start Halt
instruction instruction

Opcode Address of Operand

Instruction Format

Sign magnitude
Integer Format

Sign exponent magnitude

Floating point Format

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Actions of CPU
(Types of Instructions)
 Processor-Memory Data Transfer
 Processor-I/O Data Transfer
 Data Processing
 Arithmetic or logic operation on data
 Control
 Alter sequence of execution

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Interrupts
 An interruption of the normal sequence
of execution
 Improve processing efficiency
 Allows the processor to execute other
instructions while an I/O operation is in
progress

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Interrupts - Classes of Interrupts
 Program
 arithmetic overflow or underflow
 division by zero
 attempt to execute an illegal machine instruction
 reference outside user’s memory space
 Timer
 I/O
 Hardware Failure

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Interrupts –Interrupt Handler
 A program that determines nature of
the interrupt and performs whatever
actions are needed
 Control is transferred to this program
 Generally part of the operating system

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 Interrupts and the Instruction
Cycle

Fetch Cycle Execute Cycle Interrupts

Enabled
Fetch next Execute Check for interrupt
Start
instruction instruction and process interrupt
Interrupts
Disabled

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Interrupt Cycle
 Processor checks for interrupts
 If no interrupts, fetch the next instruction for
the current program
 If an interrupt is pending, suspend execution
of the current program, and execute the
interrupt handler

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 Program Flow of Control
without and with Interrupts
I/O Program
User Program User Program
I/O Program
(4)
(1) (1)
(4) I/O Command
WRITE WRITE
I/O Command
(2) (2) Interrupt Handler
(5)
WRITE WRITE
END (5)
(3) (3)
END
WRITE WRITE

No interrupts Interrupts
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 Simple Interrupt Processing
Hardware Software

Device controller or other

Hardware generates an interrupt
Save remainder of
process state information
Processor finished
execution of current instruction
Process interrupt

Processor signals
acknowledgement of interrupt
Restore process
state information
Processor pushes PSW
and PC onto control stack
Restore old
PSW and PC
Processor loads new
PC value based on interrupt
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Multiple Interrupts
 Two methods:
 Disable other interrupts while processing
one interrupt
 Assign priorities to different interrupts.
Interrupts at higher priority can interrupt
lower ones

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Memory
 Registers
Decreasing cost per bit
 Cache volatile
 Main memory Increasing capacity

 Electronic disk Increasing access time

 Magnetic disk Decreasing frequency of access

nonvolatile of the memory by the processor
 Optical disk
 Magnetic tapes

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Caching
 Important principle, performed at many levels in a
computer (in hardware, operating system, software)
 Information in use copied from slower to faster
storage temporarily
 Faster storage (cache) checked first to determine if
information is there
 If it is, information used directly from the cache (fast)
 If not, data copied to cache and used there

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Cache
 Invisible to operating system
 Increase the speed of memory
 Processor speed is faster than memory
speed
 Contain a portion of main memory

Word Block
Transfer Transfer Main
CPU Cache
memory
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Cache Design
 Cache size
 Block size
 Mapping function
 Determine which cache location the block will occupy
 Replacement algorithm
 Determines which block to replace
 Least-Recently-Used(LRU) algorithm
 Write policy
 When the memory write operation takes place
 Can occur every time block is updated
 Can occur only when block is replaced

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I/O Communication Techniques
 Programmed I/O
 Interrupt-Driven I/O
 Direct Memory Access (DMA)

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Programmed I/O
Issue Read
command CPU->I/O
 I/O module performs to I/O module
the action, not the
Read status of
processor I/O module
I/O -> CPU

 Sets appropriate bits in Not

ready Error
the I/O status register Check status condition
ready
 No interrupts occur
Read word from
I/O -> CPU
 Processor checks status I/O module
until operation is Write word into
complete Main memory
CPU->memory

no
Done?
yes
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Next instruction
Interrupt-Driven I/O
Issue Read CPU->I/O
command
 Processor is interrupt to I/O module
Do something
else
when I/O module
ready to exchange Read status of Interrupt
I/O module I/O -> CPU
data
 Processor is free to do Check status
Error
condition
other work
ready
 No needless waiting Read word from
I/O -> CPU
 Consumes a lot of I/O module

processor time Write word into

because every word Main memory
CPU->memory

read or written passes no

through the processor Done?
yes
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Next instruction
Direct Memory Access
 Transfer a block of data
directly to or from Issue Read CPU->DMA
memory command Do something
to I/O module else
 An interrupt is sent
Read status of Interrupt
when the task is DMA module DMA -> CPU
complete
Next instruction
 The processor is only
involved at the
beginning and end of
the transfer

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End of lecture 1

Thank you!

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