Design flow & EDA

Classic Design Flow

In general , the classic flow is

Inefficient for large digital projects

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Digital design flow

Modern Design Flow

We will use Model Sim / Questa Sim for

simulation

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Digital design flow

Introduction to FPGA

FPGA stands for Field Programmable Gate Array .

FPGA devices are used to implement different digital hardware

circuits .

Even after the circuit has been designed and implemented, FPGAs
can still be modified, updated, and completely change its
functionality to perform a completely different task than before which
make it different from ASIC design.

Top vendor : intel (Quartus) , AMD Xilinx (Vivado , ISE)

FPGA
 Introduction to FPGA

• LE ( Logic Elements ) :
• the basic repeating logic resource on an FPGA

LUT & Bitstream

A0
• Ex : Two input AND gate A1
A1 A0 F 0

0 0 0 0
F
0 1 0
0
1 0 0
1
1 1 1
FPGA
What is Verilog ?
Verilog

• Verilog is HDL (Hardware Discerption Language).

• It used to model and design digital circuits and systems.
• Similar syntax to C programming but it is not a programming language.
• We go for Verilog due to the difficulty and complexity of circuits when we do it with the Classic Flow.
• In Verilog we write a code but think Hardware … HOW?!

HDL for digital design

 Verilog
• Think : How do we write MUX 2x1 (hardware) using Verilog or pseudo code?
I0 I1 sel out
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

Hint : MUX function is to choose between two inputs using selection line.

• The answer is If condition

HDL for digital design

Numeric constants
Value Meaning Sign Radix

0 Logic zero “LOW” 'd Decimal

1 Logic one “HIGH” 'h Hexadecimal

Z High impedance (tri-state buses) 'b Binary

X Unknown value 'o Octal

\
• “X” is used by the simulators when the wires are not initialized to known value like 1 or 0

• By default, constants are not signed

Verilog Basics
Operators
~a NOT
Bitwise operators: a&b AND
• Performs bit by bit evaluation between two operands a|b OR
• 2’b01 & 2’b11 = {0&1,1&1} a^ b XOR

• ~(3’b011) = 3’b100 a ~^ b or a ^~ b XNOR

Logical operators: !a NOT

• Returns one-bit 1 or 0 (true or false) a && b AND

• !(2’b01) = 0 a || b OR
a == b If X or Z in bits returns
• “==” tests logical equality for ‘1’ and ‘0’ only all other will result in ‘X’ a != b X
• “===” tests 4-state logical equality (1,0,Z,X)
a === b Return 0 or 1 only
a !== b based on bit-by-bit
comparison

Verilog Basics
Operators &a AND
~&a NAND

Reduction operators: ^a XOR

~|a NOR
• Evaluate bit-by-bit of a vector
|a Or
• &(4’b0111) = {0&1&1&1} = 0 ^~ a or ~^a XNOR

Arithmetic operators :
• To perform arithmetic operation (- , + , * , / , %)
Arithmetic shift Logical shift
>>> , <<< >> , <<
Shift operators:
• Shift the first operand by the number specified by the second operand 3’b110 >>> 1 = 3’b111 3’b110 >> 1 = 3’b011

Relational operators:
• to compare between two operands
( == , != , < , > , <= , >= )

Verilog Basics
Verilog Essentials for
Combinational Logic
Design
Module
• Module is the basic block in Verilog consist of :
Port list
Find the
Error

Module name Declaration of ports

Keyword endmodule
Verilog Basics
Wires
• Wire represent a real and physical wire inside the module
• By default wires are 1-bit size and all inputs and outputs are wires
• We don’t declare the wires in port list as they are internal signals

• If we need to change the size

• Wire [7:0] x; // wire 8-bit bus
• Wire [9:0] y , z; // two wires 10-bit bus
• Wire [0:3] w ; wire 10-bit bus [LSB : MSB]

Concatenation : using curly braces can be used

wire [31:0] x ;
wire [7:0] a1 , a2 , a3 , a4 ;
x = { a1 , a2 , a3 , a4 };
x = {4 {a1[3:0] } , 16’h0000}; Verilog Basics
Assign
Continuous assignment
• Continuous assignment are used to describe a behavior equivalent to combinational logic
• Keyword assign is used for the assignment of wires
• Continuous assignments are continuously evaluated so when ever the RHS changes, the LFS is updated (typical
combinational logic).

• module my_and (A , B , Q);

• input A , B ;
• output Q ;
• assign Q = A & B ;
• endmodule
Verilog Basics
Assign
Continuous operator :

assign out = (sel ==1 )? first_input : second_input ;

• Is assign statement sequential or parallel ?

• The answer is that the statements are executed in parallel in structural coding and executed in order like c

code in behavioral (Next Session)

Verilog Basics
 Modeling styles
• Gate-level modeling
• The module is implemented using the built-in logic gates and the interconnection
between them

module full_adder (input A, B, Cin, output Sum, Cout); um

s1
• wire S1, S2, S3;
• xor (S1, A, B);
• and (S2, S1 , Cin);
s3 s2
• and (S3 ,A ,B);
• xor (Sum ,Cin , S1);
• or (Cout ,S2 , S3);
• endmodule Verilog Basics
 Modeling styles
• Gate-level modeling
• The module is implemented using the built-in logic gates and the interconnection
between them

module full_adder (input A, B, Cin, output Sum, Cout); um

s1
• wire S1, S2, S3;
• assign S1 = A ^ B;
• assign S2 = S1 & Cin;
s3 s2
• assign S3 = A & B;
• assign Sum = Cin ^ S1;
• assign Cout = S2 | S3;
• endmodule Verilog Basics
 Modeling styles
QUIZ
• Try to write a code for this MUX 2x1

module mux2 (input i0, i1, switch, output out);

• wire S1, S2, S3; i1 um
s1
• and (S1 , i1 , switch); switch

• nor (S2 ,switch);

• and (S3 ,S2, i0); s2
• or (out ,S1 , S3); s3
i0
• endmodule

Verilog Basics
 Modeling styles
• Data flow modeling
• Designer must know how the data flow within the design

module full_adder (input in1, in2, Cin, output S, Cout);

um

• assign {Cout,S} = in1+in2+Cin;

• endmodule

Verilog Basics
 Modeling styles
• Structural modeling
• The same as gate level modeling but doesn’t use built-in logic gates
• It include declaration and instantiation previously defined.
We need to instantiate the previous full adder to make 4-bit adder
um

module four_bit- adder (input [3:0] A , B , input cin , output [3:0]S , output Cout); // declaration of top module
• full_adder DUT (C,A,B) ;
• endmodule

Verilog Basics
 Modeling styles
• Structural modeling
module full_adder (input in1, in2, Cin, output Cout,S);
• assign {Cout,S} = in1+in2+Cin;
• endmodule
um

module add_4bit (input [3:0] A , B ,input Cin , output [3:0]S ,

out in
output Cout );
• wire C1 , C2 , C3 ;
• full_adder add1(A[0] , B[0] , Cin , C1 , S[0]);
• full_adder add2 (A[1] , B[1], C1 , C2 , S[1]);
• full_adder add3 (A[2] , B[2] ,C2 , C3, S[2]);
• full_adder add4 (A[3] , B[3] ,C3 , Cout , S[3]); Verilog Basics
• endmodule
 Modeling styles
• Structural modeling
module full_adder (input in1, in2, Cin, output Cout,S);
• assign {Cout,S} = in1+in2+Cin;
• endmodule
um

module add_4bit (input [3:0] A , B ,input Cin , output [3:0]S , output Cout );
• wire C1 , C2 , C3 ;
• full_adder add1(.in1(A[0]) , .in2(B[0]) , .Cin (Cin) , .Cout(C1) , .S(S[0]));
• full_adder add2 (.in1(A[1]) , .in2(B[1]) , .Cin (C1) , .Cout(C2) , .S(S[1]));
• full_adder add3 (.in1(A[2]) , .in2(B[2]) , .Cin (C2) , .Cout(C3) , .S(S[2]));
• full_adder add4 (.in1(A[3]) , .in2(B[3]) , .Cin (C3) , .Cout(Cout) , .S(S[3]));
• endmodule Verilog Basics
 Modeling styles
• module mux2 (input A, B, switch, output out); Quiz
• wire S1, S2, S3;
• and (S1 ,A, switch);
• nor (S2 ,switch);
• and (S3 ,S2,B);
• or (out ,S1 , S3);
• endmodule um

module mux4x1( input i0, i1 , i2, i3 , input [1:0]s , output o );

• wire z1 , z2;
• mux2 m1(i0 , i1 , s[0] , z1 ); out

• mux2 m2 ( i2, i3 , s[0] , z2);

• mux2 m3(z1 , z2 , s[1] , o);
• endmodule Verilog Basics