COMPUTER ORGANIZATION AND DESIGN 5th

The Hardware/Software Interface Edition

Chapter 3
Arithmetic for Computers
Boolean Algebra
 Boolean algebra is the basic math used
in digital circuits and computers.
 A Boolean variable takes on only 2
values: {0,1} , {T,F}, {Yes, No},
etc.
 There are 3 fundamental Boolean
operations:
 AND, OR, NOT

Chapter 3 — Arithmetic for Computers — 2

Fundamental Boolean Operations

AND OR NOT
A
Z A Z A Z
B B

Z=A*B (AB) Z=A+B Z=Ā

Truth Truth Truth

ATable
B Z ATable
B Z Table
A Z
0 0 0 0 0 0
0 1
0 1 0 0 1 1
1 0
1 0 0 1 0 1
1 1 1 1 1 1

Chapter 3 — Arithmetic for Computers — 3

Boolean Algebra
 A truth table specifies output signal logic
values for every possible combination of input
signal logic values
 In evaluating Boolean expressions, the
Operation Hierarchy is: 1) NOT 2) AND 3)
OR. Order can be superseded using
( …)
 Example: A =T,B = F,C =T,D
=T
 What is the value of Z = (A+ B)⋅(C + B
⋅D) ?
Z = (T + F)⋅(C + B⋅D) = (F + F)⋅(C + B⋅D)
= F ⋅(C + B⋅D) = F

Chapter 3 — Arithmetic for Computers — 4

Deriving Logic Expressions From Truth Tables

Light must be ON when both Truth

switches A and B are OFF, or Table:
A B Z
when both of them are ON.
0 0 1
0 1 0
Logic Function 1 0 0
SW.
A Z (light) 1 1 1

SW.
B
 What is the Boolean expression for Z?
__
Z = A.B + A.B

Chapter 3 — Arithmetic for Computers — 5

Minterms and Maxterms
 Minterms
 AND term of all input variables

 For variables with value 0, apply complements

 Maxterms
 OR factor with all input variables

 For variables with value 1, apply complements

A B Z Minterms Maxterms
0 0 1 A+B
0 1 0
1 0 0
1 1 1

Chapter 3 — Arithmetic for Computers — 6

 Minterms and Maxterms
 A function with n variables has 2n
minterms (and Maxterms) – exactly equal
to the number of rows in truth table
 Each minterm is true for exactly one
combination of inputs
 Each Maxterm is false for exactly one
combination of inputs

A B Z Minterms Maxterms
0 0 1 A+B
0 1 0
1 0 0
1 1 1

Chapter 3 — Arithmetic for Computers — 7

Equivalent Logic Expressions
 Two equivalent logic expressions can
be derived from Truth Tables:
1. Sum-of-Products (SOP) expressions:
 Several AND terms OR’d together, e.g.

ABC + ABC + ABC

2. Product-of-Sum (POS) expressions:

 Several OR terms AND’d together, e.g.
( A + B + C)( A + B + C)
Chapter 3 — Arithmetic for Computers — 8
 Rules for Deriving SOP Expressions
1. Find each row in TT for which output is
1 (rows 1 & 4)
2. For those rows write a minterm of
all input variables.
3. OR together all minterms found in (2):
Such an expression is called a
Canonical SOP

A B Z Minterms Maxterms
0 0 1 A+B
0 1 0
__
Z=AB+
1 0 0
AB
1 1 1

Chapter 3 — Arithmetic for Computers — 9

Rules for Deriving POS Expressions
1. Find each row in TT for which output is 0
(rows 2 & 3)
2. For those rows write a maxterm
3. AND together all maxterm found in (2):
Such an expression is called a Canonical
POS.
A B Z Minterms
Maxterms

0 0 1 A+ B
0 1 0 Z = (A+ B)( A+
1 0 0 B)
1 1 1

Chapter 3 — Arithmetic for Computers — 10

CSOP and CPOS
 Canonical SOP: Z = A B + AB

Canonical POS: Z = ( A + B)( A + B)
 Since they represent the same truth
table, they should be identical
Verify that
Z =A B + AB ≡(A+B)
(A+B)
 CPOS and CSOP expressions for the
same TT are logically equivalent. Both
represent the same information.

Chapter 3 — Arithmetic for Computers — 11

Activity 1
Derive SOP and POS expressions for the following TT.
A B Carry

0 0 0
0 1 0
1 0 0
1 1 1

Chapter 3 — Arithmetic for Computers — 12

 Boolean Identities
 Useful for simplifying logic equations.

2
3
4
5
6
7
8
9
10
11
12
13

Duals

13

Chapter 3 — Arithmetic for Computers — 13

Boolean Identities

 The right side is the dual of the left side

1. Duals formed by replacing
AND OR
OR
0 AND
1 1
0
2. The dual of any true statement in
Boolean algebra is also a true statement.

Chapter 3 — Arithmetic for Computers — 14

Boolean Identities
• DeMorgan’s laws very useful: 9a and 9b

A+ B =
A.B
NOR gate Alt gate rep.

AB = A+
B
Alt gate rep.
NAND gate

Chapter 3 — Arithmetic for Computers — 15

Activity 2

Proofs of some Identities:

12b: A+AB
= A+B
13a: AB + AC + BC = AB +
AC

Chapter 3 — Arithmetic for Computers — 16

Simplifying Logic Equations – Why?

A
(a) Canonical sum-of-products
B
F = A.B+ A.B+
A.B
F

F = A+
A B
B F

(b) Minimal-cost realization

Chapter 3 — Arithmetic for Computers — 17

Simplifying Logic Equations
 Simplifying logic expressions can lead to using
smaller number of gates (parts) to implement the logic
expression
 Can be done using
 Boolean Identities (algebraic)

 Karnaugh Maps (graphical)

 A minimum SOP (MSOP) expression is one that has

no more AND terms or variables than any other
equivalent SOP expression.
 A minimum POS (MPOS) expression is one that has
no more OR factors or variables than any other
equivalent POS expression.
 There may be several MSOPs of an expression

Chapter 3 — Arithmetic for Computers — 18

Example of Using Boolean Identities

 Find an MSOP for

F =XW +Y +Z(Y + XW )

= XW + Y +ZY + Z
XW
= XW (1+Z ) + Y (1+Z
)
=XW + Y

Chapter 3 — Arithmetic for Computers — 19

Activity 3

 Find an MSOP for

F =W XY Z + W XY Z + W
X YZ
= XYZ (W + W) + W X Y (Z +
Z)
= XYZ (1) + W X Y (1 )
= XYZ + W X Y
= X Y (Z + W )

Chapter 3 — Arithmetic for Computers — 20

 Digital Circuit Classification
 Combinational circuits
 Output depends only solely on the current

combination of circuit inputs

 Same set of input will always produce the same

outputs
 Consists of AND, OR, NOR, NAND, and NOT

gates
 Sequential circuits
 Output depends on the current inputs and state of

the circuit (or past sequence of inputs)

 Memory elements such as flip-flops and registers

are required to store the “state”

 Same set of input can produce completely different

outputs
Chapter 3 — Arithmetic for Computers — 21
Multiplexer
 A multiplexer (MUX) selects data from one of N
inputs and directs it to a single output, just like a
railyard switch
 4-input Mux needs 2 select lines to indicate which input to
route through
 N-input Mux needs log2(N) selection lines

Chapter 3 — Arithmetic for Computers — 22

Multiplexer (2)
 An example of 4-input Mux

4-input
I0 MUX
I0

Z I1 Z
I1
I2 S 1 S0 Z
In-1
S1 S0 0 0 I0
I3
0 1 I1
Selection
contr Functional block diagram 1 0 I2
ol 1 1 I3

Truth
Table

Chapter 3 — Arithmetic for Computers — 23

Decoder
 A decoder is a circuit element that will decode an
N-bit code.
 It activates an appropriate output line as a
function of the applied N-bit input code
Truth
3-to-8
Table
A2 A1 A0 Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z7
decoder Z0
0 0 0 1 0 0 0 0 0 0 0
A2 Z1 0 0 1 0 1 0 0 0 0 0 0
Z2 0 1 0 0 0 1 0 0 0 0 0

Z3
0 1 1 0 0 0 1 0 0 0 0
A1 1 0 0 0 0 0 0 1 0 0 0
Z4 1 0 1 0 0 0 0 0 1 0 0
Z5 1 1 0 0 0 0 0 0 0 1 0
A0 Z6 1 1 1 0 0 0 0 0 0 0 1
Functional blockZdiagram
7

Chapter 3 — Arithmetic for Computers — 24

 Why Bit

Storage ?
Flight attendant call button Call Blue light
 Press call: light turns on button
Bit
Storage
Ca
 Stays on after button ncel

released buttbutton pressed – light turns

1. Call
on on
 Press cancel: light turns Call Blue light

off button
Bit
Storage
a

Cancel
 Logic gate circuit to
2. button
implement
Call this? Q Call button released – light stays on

Cancel
a
Call Blue light
Doesn’t work. Q=1 when Call=1, Bit
but doesn’t stay 1 when Call returns button Storage
Cancel
to 0some form of “memory” in the
Need
button button pressed – light turns
circuit 3. Cancel
off

Chapter 3 — Arithmetic for Computers — 25

Bit Storage Using SR Latch
 Simplest memory elements are Latch and
Flip-Flops
 SR (set-reset) latch is an un-clocked
latch
 Output Q=1 when S=1, R=0 (set condition)
 Output Q=0 when S=0, R=1 (reset condition)
 Problem - Q is undefined if S=1 and
R=1 Call S
but ton

Blue light
Q
Cance
l R
but ton

Chapter 3 — Arithmetic for Computers — 26

Clocks
 Clock period: time interval between
pulses Freq Period
 example: period = 20 ns 100 GHz 0.01 ns
10 GHz 0.1 ns
 Clock frequency: 1/period 1 GHz 1 ns
 example: frequency = 1 / 20 ns = 50 100 MHz 10 ns
10 MHz 100 ns
MHz
 Edge-triggered clocking: all state
changes occur on a clock edge.

Chapter 3 — Arithmetic for Computers — 27

Clock and Change of State
 Clock controls when the state of a memory
element changes
 Edge-triggered clocking: all state
changes occur on a clock edge.

Chapter 3 — Arithmetic for Computers — 28

Clock Edge Triggered Bit Storage
 Flip-flop - Bit storage that stores on clock edge, not level
 D Flip-flop
 Two latches, master and slave latches.
 Output of the first goes to input of second, slave latch has
inverted clock signal (falling-edge trigger)

Chapter 3 — Arithmetic for Computers — 29

 Setup and Hold Time
 Setup time
 The minimum amount of time the data signal should

be held steady before the clock edge arrives.

 Hold time
 The minimum amount of time the data signal should

be held steady after the clock edge.

Chapter 3 — Arithmetic for Computers — 30

N-Bit Register
 Cascade N number of D flip-flops to form a
N-bit register
 An example of 8-bit register formed by
8 edge-triggered D flip-flops

Chapter 3 — Arithmetic for Computers — 31

Half Adders

 Need to add bits {0,1} of Ai and B i

 Associate
 binary bit 0 ↔ logic value F (0)
 binary bit 1 ↔ logic value T (1)

 This leads to the following truth table

A B Sum Carry
i i
SUM = A B + A B = A ⊕ B
i i+1
i i i i i i i

0 0 0 0
0 1 1 0 CARRYi+1 = Ai Bi
1 0 1 0
1 1 0 1

Chapter 3 — Arithmetic for Computers — 32

Half Adder Circuit

SUM = A B + A B = A ⊕ B
i i i i i i i

CARRYi+1 = Ai Bi

Ai
SUMi
Bi

CARRYi+
1

Chapter 3 — Arithmetic for Computers — 33

Half Adder Limitations

 Half adder circuits do not suffice for

general addition because they do not
include the carry bit from the previous
stage of addition, e.g.
Carry 01 1 0
A 0 1 1 0
B + 0 0 1 1
SUM 1 0 0 1

Chapter 3 — Arithmetic for Computers — 34

Full Adders (1-Bit ALU)

 Full adders can use the carry bit from the

previous stage of addition
Ai Bi Ci Si Ci+1
Full adder
0 0 0 0 0
Ai 0 0 1 1 0
Current Si Current 0 1 0 1 0
sum
m
0 1 1 0 1
tg Bi 1 0 0 1 0
carry-in carry-out 1 0 1 0 1
fro
previous to next
s
Ci stg
1 1 0 0 1
Ci+1
1 1 1 1 1

Chapter 3 — Arithmetic for Computers — 35

Full Adder Logic Expressions
Sum

SUM = AiBiCi +AiBiCi +AiBiCi

+AiBiCi

==AAi (B
i (BiCi +BiCi ) + Ai (BiCi +BiCi )
i ⊕Ci ) + Ai (Bi ⊕Ci )

=A i ⊕Bi ⊕Ci
Carry

Ci+1 = AiBi +Ai Bi Ci

+AiBi Ci
= AiBi +Ci (Ai Bi
+AiBi )
= AiBi +Ci (Ai ⊕Bi )
Chapter 3 — Arithmetic for Computers — 36
Full Adder Circuit
SUM = (Ai ⊕ Bi ) ⊕ Ci Ci+1 = Ai Bi + Ci (Ai ⊕ Bi )

Full adder

half adder half adder

Ai SUMi
Bi

Ci+1
Ci

Note: A full adder adds 3 bits. Can also consider as first

adding first two and then the result with the carry

Chapter 3 — Arithmetic for Computers — 37

 Enhancement to 1-bit Adder(1)

 1-bit ALU with

AND, OR, and
addition
 Supplemented with AND
and OR gates
 A multiplexer controls
which gate is connected to
the output
Operation Result
00 AND
01 OR
10 Addition

Chapter 3 — Arithmetic for Computers — 38

Enhancement to 1-bit Adder(2)

 1-bit ALU
for
subtraction
 Subtraction is
performed using 2’s
complement, i.e.

a−b=a+b
Binvert +1 CarryIn Operation Result
0 0 00 AND
0 0 01 OR
0 0 10 Addition
1 1 10 Subtraction

Chapter 3 — Arithmetic for Computers — 39

 Enhancement to 1-bit Adder(3)

 1-bit ALU for

NOR operation
 A MIPS ALU
also needs a
NOR function

( a + b) = a .
Ainvert Binvert CarryIn Operation Result
0 0 0 00 AND
1
b 1 0 00 NOR
0 0 0 01 OR
0 0 0 10 Addition
0 1 1 10 Subtraction

Chapter 3 — Arithmetic for Computers — 40

 Enhancement to 1-bit Adder(4)
 1-bit ALU for SLT
operations
 slt $s1, $s2, $s3
 If ($s2<$s3),
$s1=1,
else $s1=0
 adding one input
less
 if (a<b), set less to 1 or
if (a-b)<0, set less to 1
 If the result of
subtraction is negative,
set less to 1
 How to determine if the
result is negative? Chapter 3 — Arithmetic for Computers — 41
 Enhancement to 1-bit Adder(5)
 How to determine if
the result is
negative?
 Negative  Sign
bit value=1
 Create a new output
“Set” direct output
from the adder
and use only for slt
 An overflow
detection is included
for the most
significant bit ALU

Chapter 3 — Arithmetic for Computers — 42

N-Bit Adders (Ripple Carry)

Ai Bi
C4 C3 C2 C1
Full Ci A3 A2 A1 A0
Ci+1
Adder B3 B2 B1 B0
Si
MSB LSB

A3 B3 A2 B2 A1 B1 A0 B0

carry- C4 Stage 3
C3 Stage 2
C2 Stage 1
C1 Stage 0
C0
out FA FA FA FA 0

S3 S2 S1 S0

Note: no carry-
in

Chapter 3 — Arithmetic for Computers — 43

 Ripple Carry Adders
 4 FA’s cascaded to form a 4-bit adder
 In general, N-FA’s can be used to form a
N-bit adder
 Carry bits have to propagate from one stage
to the next. Inherent propagation delays
associated with this
 Output of each FA is therefore not stable
until the carry-in from the previous stage is
calculated

Chapter 3 — Arithmetic for Computers — 44

 32-Bit ALU
 OR and INV gates
are added to
support conditional
branch instruction,
i.e. test the result of
a-b if the result is
0.

Chapter 3 — Arithmetic for Computers — 45

32-Bit ALU

 The symbol
commonly used to
represent an ALU

 This symbol is also

used to represent an
adder, so it is normally
labeled either with
ALU or Adder

Chapter 3 — Arithmetic for Computers — 46

 §3.1 Introduction
Arithmetic for Computers
 Operations on integers
 Addition and subtraction
 Multiplication and division
 Dealing with overflow

 Floating-point real numbers

 Representation and operations

Chapter 3 — Arithmetic for Computers — 47

 §3.2 Addition and Subtraction
Integer Addition
 Example: 7 + 6

 Overflow if result out of range

 Adding +ve and –ve operands, no overflow
 Adding two +ve operands
 Overflow if result sign is 1
 Adding two –ve operands
 Overflow if result sign is 0

Chapter 3 — Arithmetic for Computers — 48

Integer Subtraction
 Add negation of second operand
 Example: 7 – 6 = 7 + (–6)
+7: 0000 0000 … 0000 0111
–6: 1111 1111 … 1111 1010
+1: 0000 0000 … 0000 0001
 Overflow if result out of range
 Subtracting two +ve or two –ve operands, no overflow
 Subtracting +ve from –ve operand
 Overflow if result sign is 0
 Subtracting –ve from +ve operand
 Overflow if result sign is 1

Chapter 3 — Arithmetic for Computers — 49

Dealing with Overflow
 Some languages (e.g., C) ignore overflow
 Use MIPS addu, addui, subu instructions
 Other languages (e.g., Ada, Fortran)
require raising an
exception/interrupt
 Use MIPS add, addi, sub
instructions
 On overflow, invoke exception/interrupt
handler
 Save PC in exception program counter (EPC)
register
 Jump to predefined handler address
 mfc0 (move from coprocessor
Chapter 3 —reg) instruction
Arithmetic for Computers — 50
 §3.3 Multiplication
Multiplication
 Start with long-multiplication approach
multiplicand
1000
multiplier × 1001
1000
0000
0000
1000
product 1001000

Length of product is
the sum of
operand lengths

Chapter 3 — Arithmetic for Computers — 51

Multiplication Hardware

Initially 0

Chapter 3 — Arithmetic for Computers — 52

Multiplication Hardware (2)

 Multiply example using flow chart algorithm

 The bit examined to determine the next step is circled in color

Chapter 3 — Arithmetic for Computers — 53

Optimized Multiplier
 Perform steps in parallel: add/shift

 One cycle per partial-product addition

 That’s ok, if frequency of multiplications is low
Chapter 3 — Arithmetic for Computers — 54
MIPS Multiplication
 Two 32-bit registers for product
 HI: most-significant 32 bits
 LO: least-significant 32-bits
 Instructions
 mult rs, rt / multu rs, rt
 64-bit product in HI/LO
 mfhi rd / mflo rd
 Move from HI/LO to rd
 Can test HI value to see if product overflows 32 bits
 mul rd, rs, rt
 Least-significant 32 bits of product – > rd

Chapter 3 — Arithmetic for Computers — 55

 §3.4 Division
Division
 Check for 0 divisor
 Long division
quotient approach
 If divisor ≤ dividend bits ct
dividend
 1 bit in quotient, subtra
 Otherwise down next
1001
1000 1001010  0 bit in quotient, bring
dividend bit
divisor
101
 Restoring division
 Do the subtract, and if remainder

1010 goes < 0, add divisor back

-  Signed division
remainder 1000  Divide using absolute values
10  Adjust sign of quotient and remainder
n-bit operands yield n-bit as required
quotient and remainder

Chapter 3 — Arithmetic for Computers — 56

Division Hardware
Initially divisor
in left half

Initially dividend

Chapter 3 — Arithmetic for Computers — 57

Division Example
Using a 4-bit version of the algorithm divide 710 by 210,
or 0000 01112 by 00102.

Chapter 3 — Arithmetic for Computers — 58

Optimized Divider

 One cycle per partial-remainder subtraction

 Looks a lot like a multiplier!
 Same hardware can be used for both

Chapter 3 — Arithmetic for Computers — 59

MIPS Division
 Use HI/LO registers for result
 HI: 32-bit remainder
 LO: 32-bit quotient

 Instructions
 div rs, rt / divu rs,
rt
 No overflow or divide-by-0 checking
 Software must perform checks if required
 Use mfhi, mflo to access result
Chapter 3 — Arithmetic for Computers — 60
 §3.5 Floating Point
Floating Point
 Representation for non-integral numbers
 Including very small and very large numbers
 Like scientific notation
 –2.34 × 1056 normalized
 +0.002 × 10 – 4 not normalized
 +987.02 × 109
 In binary
 ±1.xxxxxxx2 × 2yyyy
 Types float and double in
C
Chapter 3 — Arithmetic for Computers — 61
Floating Point Standard
 Defined by IEEE Std 754-1985
 Developed in response to divergence of
representations
 Portability issues for scientific code
 Now almost universally adopted
 Two representations
 Single precision (32-bit)
 Double precision (64-bit)

Chapter 3 — Arithmetic for Computers — 62

IEEE Floating-Point Format
single: 8 bits single: 23 bits
double: 11 bits double: 52 bits
S Exponent Fraction

x  (1)S (1 Fraction) 2(ExponentBias)

 S: sign bit (0  non-negative, 1  negative)
 Normalize significand: 1.0 ≤ |significand| < 2.0
 Always has a leading pre-binary-point 1 bit, so no need to
represent it explicitly (hidden bit)
 Significand is Fraction with the “1.” restored
 Exponent: excess representation: actual exponent
+ Bias
 Ensures exponent is unsigned
 Single: Bias = 127; Double: Bias = 1023
Chapter 3 — Arithmetic for Computers — 63
Single-Precision Range
 Exponents 00000000 and 11111111 reserved
 Smallest value
 Exponent: 00000001
 actual exponent = 1 – 127 = –126
 Fraction: 000…00  significand = 1.0
 ±1.0 × 2 –126 ≈ ±1.2 × 10 –38
 Largest value
 exponent: 11111110
 actual exponent = 254 – 127 = +127
 Fraction: 111…11  significand ≈ 2.0
 ±2.0 × 2+127 ≈ ±3.4 × 10+38

Chapter 3 — Arithmetic for Computers — 64

Double-Precision Range
 Exponents 0000…00 and 1111…11 reserved
 Smallest value
 Exponent: 00000000001
 actual exponent = 1 – 1023 = –1022
 Fraction: 000…00  significand = 1.0
 ±1.0 × 2–1022 ≈ ±2.2 × 10–308
 Largest value
 Exponent: 11111111110
 actual exponent = 2046 – 1023 = +1023
 Fraction: 111…11  significand ≈ 2.0
 ±2.0 × 2+1023 ≈ ±1.8 × 10+308

Chapter 3 — Arithmetic for Computers — 65

Floating-Point Precision
 Relative precision
 all fraction bits are significant
 Single: approx 2 – 2 3
 Equivalent to 23 × log102 ≈ 23 × 0.3 ≈ 6 decimal
digits of precision
 Double: approx 2 – 5 2
 Equivalent to 52 × log102 ≈ 52 × 0.3 ≈ 16 decimal
digits of precision

Chapter 3 — Arithmetic for Computers — 66

Floating-Point Example
 Represent –0.75
 –0.75 = (–1) 1 × 1.12 × 2 – 1
 S=1
 Fraction = 1000…00 2
 Exponent = – 1 + Bias
 Single: – 1 + 127 = 126 = 011111102
 Double: – 1 + 1023 = 1022 = 011111111102
 Single: 1011111101000…00
 Double: 1011111111101000…00

Chapter 3 — Arithmetic for Computers — 67

Floating-Point Example
 What number is represented by the single-
precision float
11000000101000…00
 S=1
 Fraction = 01000…00 2
 Exponent = 100000012 = 129
 x = (–1) 1 × (1 + 012) × 2(129 – 127)

= (–1) × 1.25 × 22
= –5.0

Chapter 3 — Arithmetic for Computers — 68

Floating-Point Addition
 Consider a 4-digit decimal example
 9.999 × 101 + 1.610 × 10 – 1
 1. Align decimal points
 Shift number with smaller exponent
 9.999 × 101 + 0.016 × 101
 2. Add significands
 9.999 × 101 + 0.016 × 101 = 10.015 × 101
 3. Normalize result & check for over/underflow
 1.0015 × 102
 4. Round and renormalize if necessary
 1.002 × 102

Chapter 3 — Arithmetic for Computers — 69

Floating-Point Addition

Chapter 3 — Arithmetic for Computers — 70

Floating-Point Addition
 Now consider a 4-digit binary example
 1.0002 × 2 – 1 + –1.110 2 × 2 – 2 (0.5 + –0.4375)
 1. Align binary points
 Shift number with smaller exponent
 1.0002 × 2 – 1 + –0.111 2 × 2 – 1
 2. Add significands
 1.0002 × 2 – 1 + –0.111 2 × 2 – 1 = 0.0012 × 2 – 1
 3. Normalize result & check for over/underflow
 1.0002 × 2 – 4 , with no over/underflow
 4. Round and renormalize if necessary
 1.0002 × 2 – 4 (no change) = 0.0625

Chapter 3 — Arithmetic for Computers — 71

FP Adder Hardware
 Much more complex than integer adder
 Doing it in one clock cycle would take too
long
 Much longer than integer operations
 Slower clock would penalize all instructions
 FP adder usually takes several cycles
 Can be pipelined

Chapter 3 — Arithmetic for Computers — 72

FP Adder Hardware

Step 1

Step 2

Step 3

Step 4

Chapter 3 — Arithmetic for Computers — 73

Floating-Point Multiplication
 Consider a 4-digit decimal example
 1.110 × 1010 × 9.200 × 10 – 5
 1. Add exponents
 For biased exponents, subtract bias from sum
 New exponent = 10 + – 5 = 5
 2. Multiply significands
 1.110 × 9.200 = 10.212  10.212 × 105
 3. Normalize result & check for over/underflow
 1.0212 × 106
 4. Round and renormalize if necessary
 1.021 × 106
 5. Determine sign of result from signs of operands
 +1.021 × 106

Chapter 3 — Arithmetic for Computers — 74

Floating-Point Multiplication(2)

Chapter 3 — Arithmetic for Computers — 75

Floating-Point Multiplication(3)
 Now consider a 4-digit binary example
 1.0002 × 2 – 1 × –1.110 2 × 2 – 2 (0.5 × –0.4375)
 1. Add exponents
 Unbiased: – 1 + – 2 = – 3
 Biased: (–1 + 127) + (–2 + 127) = – 3 + 254 – 127 = – 3 + 127
 2. Multiply significands
 1.0002 × 1.1102 = 1.1102  1.1102 × 2 – 3
 3. Normalize result & check for over/underflow
 1.1102 × 2 – 3 (no change) with no over/underflow
 4. Round and renormalize if necessary
 1.1102 × 2 – 3 (no change)
 5. Determine sign: +ve × –ve  –ve
 –1.110 2 × 2 – 3 = –0.21875

Chapter 3 — Arithmetic for Computers — 76

FP Arithmetic Hardware
 FP multiplier is of similar complexity to FP
adder
 But uses a multiplier for significands instead of
an adder
 FP arithmetic hardware usually does
 Addition, subtraction, multiplication, division,
reciprocal, square-root
 FP  integer conversion
 Operations usually takes several cycles
 Can be pipelined

Chapter 3 — Arithmetic for Computers — 77

FP Instructions in MIPS
 FP hardware is coprocessor 1
 Adjunct processor that extends the ISA
 Separate FP registers
 32 single-precision: $f0, $f1, … $f31
 Paired for double-precision: $f0/$f1, $f2/$f3, …
 Release 2 of MIPs ISA supports 32 × 64-bit FP reg’s
 FP instructions operate only on FP registers
 Programs generally don’t do integer ops on FP data,
or vice versa
 More registers with minimal code-size impact
 FP load and store instructions
 lwc1, ldc1, swc1, sdc1
 e.g., ldc1 $f8, 32($sp)

Chapter 3 — Arithmetic for Computers — 78

FP Instructions in MIPS
 Single-precision arithmetic
 add.s, sub.s, mul.s, div.s
 e.g., add.s $f0, $f1, $f6
 Double-precision arithmetic
 add.d, sub.d, mul.d, div.d
 e.g., mul.d $f4, $f4, $f6
 Single- and double-precision comparison
 c.xx.s, c.xx.d (xx is eq, lt, le, … )
 Sets or clears FP condition-code bit
 e.g. c.lt.s $f3, $f4
 Branch on FP condition code true or false
 bc1t, bc1f
 e.g., bc1t TargetLabel

Chapter 3 — Arithmetic for Computers — 79

FP Example: °F to °C
 C code:
float f2c (float fahr) {
return ((5.0/9.0)*(fahr - 32.0));
}
 fahr in $f12, result in $f0, literals in global

memory space
 Compiled MIPS code:
f2c: lwc1 $f16, const5($gp)
lwc2 $f18, const9($gp)
div.s $f16, $f16, $f18
lwc1 $f18, const32($gp)
sub.s $f18, $f12, $f18
mul.s $f0, $f16, $f18
jr $ra
Chapter 3 — Arithmetic for Computers — 80
 §3.9 Fallacies and Pitfalls
Right Shift and Division
 Left shift by i places multiplies an integer
by 2i
 Right shift divides by 2i?
 Only for unsigned integers
 For signed integers
 Arithmetic right shift: replicate the sign bit
 e.g., – 5 / 4
 111110112 >> 2 = 111111102 = – 2
 Rounds toward – ∞
 c.f. 111110112 >>> 2 = 001111102 = +62

Chapter 3 — Arithmetic for Computers — 81

Concluding Remarks
 ISAs support arithmetic
 Signed and unsigned integers
 Floating-point approximation to reals
 Bounded range and precision
 Operations can overflow and underflow
 MIPS ISA
 Core instructions: 54 most frequently used
 100% of SPECINT, 97% of SPECFP
 Other instructions: less frequent

Chapter 3 — Arithmetic for Computers — 82

Acknowledgement
The slides are adopted from Computer
Organization and Design, 5th Edition
by David A. Patterson and John L. Hennessy
2014, published by MK (Elsevier)

Chapter 3 — Arithmetic for Computers — 83