COMPUTER ORGANIZATION AND DESIGN 5th

The Hardware/Software Interface Edition

Chapter 4
The
Processor
 §4.1 Introduction
Introduction
 CPU performance factors
 Instruction count
 Determined by ISA and compiler
 CPI and Cycle time
 Determined by CPU hardware
 We will examine two MIPS implementations
 A simplified version
 A more realistic pipelined version
 Simple subset, shows most aspects
 Memory reference: lw, sw
 Arithmetic/logical: add, sub, and, or, slt
 Control transfer: beq, j

Chapter 4 — The Processor — 2

Instruction Execution
 PC  instruction memory, fetch instruction
 Register numbers  register file, read registers
 Depending on instruction class
 Use ALU to calculate
 Arithmetic result
 Memory address for load/store
 Branch target address
 Access data memory for load/store
 PC  target address or PC + 4

Chapter 4 — The Processor — 3

CPU Overview

Chapter 4 — The Processor — 4

Multiplexers
 Can’t just join
wires together
 Use
multiplexers

Chapter 4 — The Processor — 5

Control

Chapter 4 — The Processor — 6

 §4.2 Logic Design Conventions
Logic Design Basics
 Information encoded in binary
 Low voltage = 0, High voltage = 1
 One wire per bit
 Multi-bit data encoded on multi-wire buses
 Combinational element
 Operate on data
 Output is a function of input
 State (Sequential) elements
 Store information

Chapter 4 — The Processor — 7

Combinational Elements
 AND-gate  Adder
 Y =A&B  Y=
A A+ B A
Y + Y
B
B

 Multiplexer  Arithmetic/Logic Unit

 Y = S ? I 1 : I0  Y = F(A, B)
M
I0
u A
I1 Y
AL Y
x
U
S B
F
Chapter 4 — The Processor — 8
Multiplexors(1)

A two-input multiplexor has two data inputs (A and B)

labeled 0 and 1, one selector input (S), and an output C.

Chapter 4 — The Processor — 9

 Multiplexors(2)
 A multiplexor is
arrayed 32
times to
perform a
selection
between two
32-bit inputs.
 One data
selection signal
used for all 32
1-bit
multiplexors.

Chapter 4 — The Processor — 10

Sequential Elements
 Register: stores data in a circuit
 Uses a clock signal to determine when to
update the stored value
 Edge-triggered: update when Clk changes
from 0 to 1

Clk
D Q
D

Clk
Q

Chapter 4 — The Processor — 11

 Sequential Elements
 Register with write control
 Only updates on clock edge when write
control input is 1
 Used when stored value is required later

Clk

D Q Write

Write D
Clk
Q

Chapter 4 — The Processor — 12

Clocking Methodology
 Combinational logic transforms data during
clock cycles
 Between clock edges
 Input from state elements, output to state
element
 Longest delay determines clock period

Chapter 4 — The Processor — 13

 §4.3 Building a Datapath
Building a Datapath
 Datapath
 Elements that process data and addresses in
the CPU
 Registers, ALUs, mux’s, memories, …
 We will build a MIPS datapath
incrementally
 Refining the overview design

Chapter 4 — The Processor — 14

Instruction Fetch

Increment by
4 for next
32-bit instruction
register

A portion of the datapath used for fetching instructions and

incrementing the program counter. The fetched instruction is used
by other parts of the datapath.
Chapter 4 — The Processor — 15
R-Format Instructions
 Read two register operands
 Perform arithmetic/logical operation
 Write register result

Chapter 4 — The Processor — 16

Load/Store Instructions
 Read register operands
 Calculate address using 16-bit offset
 Use ALU, but sign-extend offset
 Load: Read memory and update register
 Store: Write register value to memory

Chapter 4 — The Processor — 17

Branch Instructions
 Read register operands
 Compare operands
 Use ALU, subtract and check Zero output
 Calculate target address
 Sign-extend displacement
 Shift left 2 places (word
displacement)
 Add to PC + 4
 Already calculated by
instruction fetch

Chapter 4 — The Processor — 18

Branch Instructions
Just
re-routes
wire
s

Sign-bit wire
replicated

Chapter 4 — The Processor — 19

Composing the Elements
 Simple data path does one instruction in
one clock cycle
 Each datapath element can only do one
function at a time
 Hence, we need separate instruction and data
memories
 Use multiplexers where alternate data
sources are used for different instructions

Chapter 4 — The Processor — 20

R-Type/Load/Store Datapath

Chapter 4 — The Processor — 21

Full Datapath

Chapter 4 — The Processor — 22

 §4.4 A Simple Implementation Scheme
ALU Control
 ALU used for
 Load/Store: F = add
 Branch: F = subtract
 R-type: F depends on funct field
ALU control Function
0000 AND
0001 OR
0010 add
0110 subtract
0111 set-on-less-than
1100 NOR

Chapter 4 — The Processor — 23

ALU Control (2)
 Assume 2-bit ALUOp derived from opcode
 Combinational logic derives ALU control

opcode ALUOp Operation funct ALU function ALU control

lw 00 load word XXXXXX add 0010
sw 00 store word XXXXXX add 0010
beq 01 branch equal XXXXXX subtract 0110
R-type 10 add 100000 add 0010
subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
set-on-less-than 101010 set-on-less-than 0111

Chapter 4 — The Processor — 24

The Main Control Unit
 Control signals derived from instruction

R-type 0 rs rt rd shamt funct

31:26 25:21 20:16 15:11 10:6 5:0

Load/ 35 or 43 rs rt address
Store
31:26 25:21 20:16 15:0

Branch 4 rs rt address
31:26 25:21 20:16 15:0

opcode always read, write for sign-extend

read except R-type and add
for load and load

Chapter 4 — The Processor — 25

The Main Control Unit (2)

Chapter 4 — The Processor — 26

The Main Control Unit (3)

Chapter 4 — The Processor — 27

Datapath With Control

Chapter 4 — The Processor — 28

 Datapath With Control (2)

• The setting of the control lines is completely determined by the opcode fields of the
instruction.
• The first row of the table corresponds to the R-format instructions (add, sub, AND,
OR, and slt). For all these instructions, the source register fields are rs and rt, and
the destination register field is rd; this defines how the signals ALUSrc and RegDst
are set. R-type instruction writes a register (Reg Write = 1), but neither reads nor
writes data memory.
• When the Branch control signal is 0, the PC is unconditionally replaced with PC +
4; otherwise, the PC is replaced by the branch target if the Zero output of the ALU
is also high.
• The ALUOp field for R-type instructions is set to 10 to indicate that the ALU
control should be generated from the funct field.

Chapter 4 — The Processor — 29

R-Type Instruction

Chapter 4 — The Processor — 30

R-Type Instruction (2)
For example, add $t1,$t2,$t3

Four steps to execute the instruction in one clock cycle

1. The instruction is fetched, and the PC is incremented
2. Registers $t2 and $t3 are read from the register file. Also,
the main control unit computes the setting of the control
lines during this step
3. The ALU operates on the data read from the register file,
using the function code (bits 5:0, funct field) to generate the
ALU function
4. The result from the ALU is written into the register file
using bits 15:11 of the instruction to select the destination
register ($t1)

Chapter 4 — The Processor — 31

Load Instruction

Chapter 4 — The Processor — 32

Load Instruction (2)
For example, lw $t1, offset($t2)

Five steps to execute the instruction in one clock cycle

1. Instruction is fetched from the instruction memory and PC
is Incremented
2. Register ($t2) value is read from the register file
3. ALU computes the sum of the value read from register file
and sign-extended offset
4. Sum from ALU is used as the address for the data
memory
5. Data from the memory unit is written into register file.
Register destination is given by bits 20:16 of the
instruction ($t1)

Chapter 4 — The Processor — 33

Branch-on-Equal Instruction

Chapter 4 — The Processor — 34

Branch-on-Equal Instruction (2)
For example, beq $t1, $t2, offset

Four steps to execute the instruction in one clock cycle

1. An instruction is fetched from instruction memory
and PC is incremented
2. Register ($t2) value is read from the register file
3. ALU performs a subtract on the data values read from
the register file. PC + 4 is added to sign- extended
offset shifted left by two; result is branch target
address
4. Zero result from ALU is used to decide which adder
result to store into PC

Chapter 4 — The Processor — 35

Implementing Jumps
Jump 2 address
31:26 25:0

 Jump uses word address

 Update PC with concatenation of
 Top 4 bits of old PC
 26-bit jump address
 And 00 at the right
 Need an extra control signal decoded from
opcode
Chapter 4 — The Processor — 36
Datapath With Jumps Added

Chapter 4 — The Processor — 37

Performance Issues
 Longest delay determines clock period
 Critical path: load instruction
 Instruction memory  register file  ALU 
data memory  register file
 Not feasible to vary period for different
instructions
 Violates design principle
 Making the common case fast
 We will improve performance by
pipelining
Chapter 4 — The Processor — 38
 §4.5 An Overview of Pipelining
Pipelining Analogy
 Pipelined laundry: overlapping execution
 Parallelism improves performance

 Four loads:
 Speedup
= 8/3.5 = 2.3
 Non-stop:
 Speedup
=
2n/(0.5n+
1.5) ≈ 4
= number
of stages
Chapter 4 — The Processor — 39
MIPS Pipeline
 Five stages, one step per stage
1. IF: Instruction fetch from memory
2. ID: Instruction decode & register
read
3. EX: Execute operation or calculate
address
4. MEM: Access memory operand
5. WB: Write result back to register

Chapter 4 — The Processor — 40

 Pipeline Performance
 Assume time for stages is
 100ps for register read or write
 200ps for other stages
 Compare pipelined datapath with single-cycle
datapath

Instr Instr fetch Register ALU op Memory Register Total time

read access write
lw 200ps 100 ps 200ps 200ps 100 ps 800ps
sw 200ps 100 ps 200ps 200ps 700ps
R-format 200ps 100 ps 200ps 100 ps 600ps
beq 200ps 100 ps 200ps 500ps

Chapter 4 — The Processor — 41

Pipeline Performance
Single-cycle (Tc= 800ps)

Pipelined (Tc= 200ps)

Chapter 4 — The Processor — 42

Pipeline Speedup
 If all stages are balanced
 i.e., all take the same time
 Time between
instructionspipelined
= Time between instructionsnonpipelined
Number of stages
 If not balanced, speedup is less
 Speedup due to increased throughput
 Latency (time for each instruction) does not
decrease
Chapter 4 — The Processor — 43
Pipelining and ISA Design
 MIPS ISA designed for pipelining
 All instructions are 32-bits
 Easier to fetch and decode in one cycle
 c.f. x86: 1- to 17-byte instructions
 Few and regular instruction formats
 Can decode and read registers in one step
 Load/store addressing
 Can calculate address in 3rd stage, access memory in 4th
stage
 Alignment of memory operands
 Memory access takes only one cycle

Chapter 4 — The Processor — 44

Hazards
 Situations that prevent starting the next
instruction in the next cycle
 Structure hazards
 A required resource is busy
 Data hazard
 Need to wait for previous instruction to
complete its data read/write
 Control hazard
 Deciding on control action depends on
previous instruction

Chapter 4 — The Processor — 45

Structure Hazards
 Conflict for use of a resource
 In MIPS pipeline with a single memory
 Load/store requires data access
 Instruction fetch would have to stall for that
cycle
 Would cause a pipeline “bubble”
 Hence, pipelined datapaths require
separate instruction/data memories
 Or separate instruction/data caches

Chapter 4 — The Processor — 46

Data Hazards
 An instruction depends on completion of
data access by a previous instruction
 add $s0, $t0, $t1
sub $t2, $s0, $t3

Chapter 4 — The Processor — 47

Forwarding (aka Bypassing)
 Use result when it is computed
 Don’t wait for it to be stored in a register
 Requires extra connections in the datapath

Chapter 4 — The Processor — 48

Load-Use Data Hazard
 Can’t always avoid stalls by forwarding
 If value not computed when needed
 Can’t forward backward in time!

Chapter 4 — The Processor — 49

Code Scheduling to Avoid Stalls
 Reorder code to avoid use of load result in the
next instruction
 C code for A = B + E; C = B + F;

lw $t1, 0($t0) lw $t1, 0($t0)

lw $t2, 4($t0) lw $t2, 4($t0)
stall add $t3, $t1, $t2 lw $t4, 8($t0)
sw 12($t0) add $t3, $t1, $t2
$t3, 8($t0) sw $t3, 12($t0)
stall lw $t4, $t1, $t4 add $t1, $t4
add $t5, 16($t0) $t5, sw 16($t0)
swcycles
13 $t5, 11 cycles
$t5,
Chapter 4 — The Processor — 50
Control Hazards
 Branch determines flow of control
 Fetching next instruction depends on branch
outcome
 Pipeline can’t always fetch correct instruction
 Still working on ID stage of branch
 In MIPS pipeline
 Need to compare registers and compute
target early in the pipeline
 Add hardware to do it in ID stage

Chapter 4 — The Processor — 51

Stall on Branch
 Wait until branch outcome determined
before fetching next instruction

Chapter 4 — The Processor — 52

Branch Prediction
 Longer pipelines can’t readily determine
branch outcome early
 Stall penalty becomes unacceptable
 Predict outcome of branch
 Only stall if prediction is wrong
 In MIPS pipeline
 Can predict branches not taken
 Fetch instruction after branch, with no delay

Chapter 4 — The Processor — 53

MIPS with Predict Not Taken

Prediction
correct

Prediction
incorrect

Chapter 4 — The Processor — 54

More-Realistic Branch Prediction
 Static branch prediction
 Based on typical branch behavior
 Example: loop and if-statement branches
 Predict backward branches taken
 Predict forward branches not taken
 Dynamic branch prediction
 Hardware measures actual branch behavior
 e.g., record recent history of each branch
 Assume future behavior will continue the trend
 When wrong, stall while re-fetching, and update history

Chapter 4 — The Processor — 55

Pipeline Summary
The BIG Picture

 Pipelining improves performance by

increasing instruction throughput
 Executes multiple instructions in parallel
 Each instruction has the same latency
 Subject to hazards
 Structure, data, control
 Instruction set design affects complexity of
pipeline implementation
Chapter 4 — The Processor — 56
Acknowledgement
The slides are adopted from Computer
Organization and Design, 5th Edition
by David A. Patterson and John L. Hennessy
2014, published by MK (Elsevier)

Chapter 4 — The Processor — 57