NATIONAL UNIVERSITY OF HO CHI MINH CITY

UNIVERSITY OF INFORMATION TECHNOLOGY

FACULTY OF COMPUTER ENGINEERING

LECTURE

Subject: VERILOG
Hardware Description Language
Chapter1: Introduction

Lecturer: Lam Duc Khai

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 Agenda

1. Chapter 1: Introduction ( Week1)

2. Chapter 2: Fundamental concepts (Week1)
3. Chapter 3: Modules and hierarchical structure (Week2)
4. Chapter 4: Primitive Gates – Switches – User defined primitives
(Week2)
5. Chapter 5: Structural model (Week3, Week4)
6. Chapter 6: Behavioral model – Combination circuit and
Sequential circuit (Week4, 5)
7. Chapter 7: Tasks and Functions (Week6)
8. Chapter 8: State machines (Week6)
9. Chaper 9: Testbench and verification (Week7)
10. Project presentation ( Week7, Week8)
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 Contents

Chapter 1: Introduction
 Requirements – Projects – Scores
 Verilog – What and Why ?
 CAD flow

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 Requirement

 Must be punctual on both class and laboratory. An

excess of 15 minutes is not accepted for any reason.
 Class : Start at 7:30 AM on Monday.
 Laboratory : Start at 1:00 PM as schedule.
 Project :
 Submit strictly as the deadline through email:
[email protected].
 Name of project file and email subject must abide by the
following format, any others format are not accepted:
“Project name_maingroup_subgroup_date”

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 Projects

• Projects :
– Group1: A Floating Point Unit for Numerical Calculations.
– Group2: Real-time Light-Saber Generator
– Group3: Real-time Video Processing
– Group4: FPGA Video Game
– Group5: Real-time Face Detection
– Group6: Gestural Interface for Image Browsing
– Group7: Gesture Recognition Remote Control
– Group8: Hardware Platform for JPEG
Compression/Decompression
Reference : http://web.mit.edu/6.111/www/
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 Scores

• Grading system:
– Final exam : 50 %
– Mid-exam : 20 %
– Laboratory : 20%
– Exercises: 10%
• Note: These above scores will only be valid if
student attends the laboratory class fully.

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 Verilog learning “tips”
• Verilog is essentially a programming language – similar to C with some
Pascal-like constructs
• The best way to learn any programming language is from live code
• We will get you started by going through several example programs and
explaining the key concepts
• We will not try to teach you the syntax line-by-line: pick up what you need
from the books and on-line tutorials
• Tip: Start by copying existing programs and modifying them incrementally
making sure you understand the output behavior at each step
• Tip: The best way to understand and remember a construct or keyword is to
experiment with it in code, not by reading about it
• We shall not design at the switch (transistor) level in this course – the lowest
level we shall reach is the gate level. The transistor level is more appropriate
for an electronics-oriented course

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 History

• HDL History
• 1970s: First HDLs
• Late 1970s: VHDL
• VHDL = VHSIC HDL = Very High Speed Integrated Circuit HDL
• VHDL inspired by programming languages of the day (Ada)
• 1980s:
• Verilog first introduced
• Verilog inspired by the C programming language
• VHDL standardized
• 1990s:
• Verilog standardized (Verilog-1995 standard)
• 2000s:
• Continued evolution (Verilog-2001 standard)
• Both VHDL and Verilog evolving, still in use today

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 Why To Represent Hardware?

• If you’re going to design a computer, you need to write down the design so
that:
• You can read it again later
• Someone else can read and understand it
• It can be simulated and verified
• Even software people may read it!
• It can be synthesized into specific gates
• It can be built and shipped and make money

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 How To Represent Hardware?
• Draw schematics
• Hand-drawn
• Machine-drawn
• Write a netlist
Z52BH I1234 (N123, N234, N4567);
• Write primitive Boolean equations
AAA = abc DEF + ABC def
• Use a Hardware Description Language (HDL)
assign overflow = c31 ^ c32;

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 Custom design vs System design
– Custom design:
• Small design . For instance : RAM, ROM, ALU, …
• High performance
• Designed by schematic or SPICE netlist
• Very time consuming to design (timing, power,… verification by
simulation)
– System design:
• Large and complex design , system level ((millions to billions of gates). For
instance : Chip, Micro processor, CPU, …
• Lower performance
• Designed by HDL.
• Less design time  more productivity.

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 HDL-Advantages
– Describe complex designs (millions to billions of gates)
– Input to synthesis tools (generated circuits)
– Design exploration with simulation with less time consuming.
– Support for structure and instantiation
– Support for describing bit-level behavior
– Support for timing
– Support for concurrency

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 HDL-Disadvantages
– Much depends on Synthesis tools.
– Hard to optimize design.

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 Verilog vs. VHDL
– Verilog is relatively simple and close to C
– VHDL is complex
– For commercial products, it’s Verilog, Verilog has 60% of the world digital
design market (larger share in US)
– For large projects such as defense and telecommunication projects from
government / aerospace work, it’s VHDL

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 “Keep in heart”

• HDLs are not “programming languages”

• When coding in an HDL, it is important to remember that you are
specifying hardware that executes in parallel rather than software that
executes sequentially.
• In a program, we start at the beginning (e.g. “main”), and we proceed
sequentially through the code as directed. The program represents an
algorithm, a step-by-step sequence of actions to solve some problem
• Hardware is all active at once; there is no starting point. Everything
happens concurrently.
• “Sequential design in HDL differs from sequential executive commands in
programming languages”.

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 CAD flow
 Evolution of Computer Aided Design (CAD)
Vacuum tubes and transitors

Integrated circuit (IC)

BY HAND
Increase to use CAD
More sophisticated

Small scale integration (SSI) Gate count was small

Medium scale integration (MSI) Hundreds of gates

Large scale integration (LSI) EDA began evolve

Thousands of gates
in logic simulation
Very large scale integration
(VLSI) >100,000 transistors EDA was critical
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 CAD flow (cont’d)
 Computer Aided Design vs Manual Design

Verilog design Schematic design

Pros - Easy to implement function - Customer design

- Simulate to verify function quickly - Be able to optimize performance, power
due to simple netlist and area of design.
- Generate schematic and layout
automatically by using CAD tools.
- Helpful for system synthesis
Cons - No optimality for performance, - Must be master on IC design
power and area of design. - Take time to simulate to verify function
due to big and complicated netlist.
- Hard to design for system level
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 CAD flow (cont’d)
 CAD Design Flow: Design Specification

Behavior Description

Pre-synthesis verification

Compilation and Synthesis

Routing and Placement

Timing analyis

Post-synthesis verification

Physical layout

Chip 18
 CAD flow (cont’d)
 Design specification: Design Specification

Behavior Description
+ Describe the FUNCTIONALITY, INTERFACE, and OVERALL ARCHITECTURE
+ Do not need to think about HOW to implement
Pre-synthesis verification

Compilation and Synthesis

Routing and Placement

Timing analyis

Post-synthesis verification

Physical layout

Chip 19
 CAD flow (cont’d)
Design Specification
 Behavior Description:
Behavior Description

+ Analyze the design in terms of FUNCTIONALITY, PERFORMANCE,

Pre-synthesis verification
COMPLIANCE to standards, and OTHER high-level issues
Compilation
+ Often written with HDLs or EDA tools (combineand
HDLsSynthesis
and object oriented languages
such as C++)
Routing
Behavior description for and
design Placement in Verilog
specification

module design(…); comp 1 U1(…);

Timing analyis always (posedge clk)
assign … comp2 U2(…); begin …end
Post-synthesis verification
always … … if (…) bus = w;
compi (…) compn Un(…);
Physical layout else …
endmodule
Chip
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 CAD flow (cont’d)
 Pre-synthesis Design Specification
verification:
Behavior Description

Pre-synthesis verification

+ Check design function flaws that may Compilation

cause by ambiguous
and Synthesis
problem specification,
designer errors, or incorrect use of parts in the design.
Routing and
+ Done by simulation (presynthesis simulation), Placement
assertion verification with testbench
definition or input waveform.
Timing analyis
+ Do not consider gate, propagation delay, hazards, glitches, race conditions, setup and
hold violations, and other related timing issues.
Post-synthesis verification

Physical layout

Chip 21
 CAD flow (cont’d)
 Function verification with testbench:

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 CAD flow (cont’d)
 Function verification with testbench:

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 CAD flow (cont’d)
 Function verification with input waveform:

Define input waveform manually

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 CAD flow (cont’d)
 Compilation and Design Specification
Synthesis:
Behavior Description

Pre-synthesis verification

Compilation and Synthesis

-Compilation and systhesis : automaticRouting

hardware
and
generation
Placementfrom Verilog description.
-Analysis phase: Analyze and translate the functional specification ( Verilog description)
Timing
the specification of hardware, technology files withanalyis
detailed timing into the uniform
format data.
Post-synthesis verification
-Synthesis phase: Combine all uniform format data above together and generate the
corresponding logic.
Physical layout

Chip 25
 CAD flow (cont’d)
 Compilation and Synthesis
Determine which
logic gates, elements
to implement the
boolean expressions

A set of boolean expressions A set of optimized boolean expressions,

or a netlist of basic gates. tabular logic representations or primitive
gate netlists. 26
 CAD flow (cont’d)
 Routing and Design Specification
Placement:
Behavior Description

Pre-synthesis verification

Compilation and Synthesis

Routing and Placement

-Decide the placement of cells and connection

Timing analyis
between inputs and outputs of these cells
for the target hardware ( ASIC, FPGA).
-Output is a complete netlist of Post-synthesis
target hardwareverification
including components, wiring delays of
each interconnection, and load effects on gates.
Physical layout

Chip 27
 CAD flow (cont’d)
 Timing analysis: Design Specification

Behavior Description

Pre-synthesis verification

Compilation and Synthesis

Routing and Placement

Timing analyis

-Generates worst-case delays, clock speed, delay

Post-synthesis paths and setup times, hold times.
verification
-Designers use these information to optimize design such as changing routing and
placement. Physical layout

Chip 28
 CAD flow (cont’d)
 Post-synthesis Design Specification
verification:
Behavior Description

Pre-synthesis verification

Compilation and Synthesis

Routing and Placement

Timing analyis

Post-synthesis verification

-Using netlist from routing and placement phase

Physical as the input for post-synthesis simulation.
layout
-Verify clock frequency, race condition, hazzard condition, function and delay timings
Chip
such as setup times, hold times, access times, output hold times ... 29
 CAD flow (cont’d)
 Physical layout: Design Specification

Behavior Description

Pre-synthesis verification

Compilation and Synthesis

Routing and Placement

Timing analyis
-Programming for FPGA
-Layout for ASIC manufacturing
Post-synthesis
( poly-silicon,verification
diffusion, metal connection…)

Physical layout

Chip 30
 CAD flow (cont’d)
 Fabrication Design Specification
for Chip:
Behavior Description

Pre-synthesis verification

Compilation and Synthesis

Routing and Placement

Timing analyis

Post-synthesis verification

-Fabrication for design on wafer Physical layout

Chip 31
 CAD flow (cont’d)
 Summary:
– HDLs are now the dominant method for large digital designs
– Syntax is similar to C language  easy to learn and easy to use
– Allows different levels of abstraction (switches, gates, RTL, or behavioral
code) to be mixed in the same level
– Most popular logic synthesis tools support Verilog
– Allows the user to write custom C code to interact with internal data structures
of Verilog by using PLI (Programming Language Interface)

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END

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