Unit 2- ARM Processor fundamentals

RISC and ARM Design philosophy

ARM core Dataflow model
programming model
processor states and operating modes
exceptions and interrupts
ARM pipeline
ARM instruction set
Assembler rules and Directives
load/store architecture
ARM-THUMB interworking
programming
 RISC vs. CISC

Reduced Instruction Set Computer (RISC)

• Compact, uniform instructions
• Facilitates pipelining
• More lines of code
• Allows effective compiler optimization
Complex Instruction Set Computer (CISC)
• Many addressing modes and instructions;
• High code density.
• Often require manual optimization of assembly code for embedded
systems
 ARM Ltd

■ Founded in November 1990

■ Spun out of Acorn Computers

■ Designs the ARM range of RISC processor cores

■ Licenses ARM core designs to semiconductor partners who
fabricate and sell to their customers.
■ ARM does not fabricate silicon itself

■ Also develop technologies to assist with the design-in of the

ARM architecture
■ Software tools, boards, debug hardware, application software,
bus architectures, peripherals etc
ARM Powered Products
 RISC Design philosophy

• The ARM core uses a RISC architecture.

• RISC is a design philosophy aimed at delivering simple but powerful
instructions that execute within a single cycle at a high clock speed.
• The RISC philosophy concentrates on reducing the complexity of
instructions performed by the hardware because it is easier to
provide greater flexibility and intelligence in software rather than
hardware.
• As a result, a RISC design places greater demands on the compiler.
• In contrast, the traditional complex instruction set computer (CISC)
relies more on the hardware for instruction functionality, and
consequently the CISC instructions are more complicated.
Major differences
The RISC philosophy is implemented with four major design rules
1. Instructions: RISC processors have a reduced number of classes.
• These classes provide simple operations that can each execute in a single
cycle.
• The compiler or programmer synthesizes complicated operations (for
example, a divide operation) by combining several simple instructions.
Each instruction is a fixed length to allow the pipeline to fetch future
instructions before decoding the current instruction.
1. Pipelines- The processing of instructions is broken down into smaller units
that can be executed in parallel by pipelines.
• Ideally the pipeline advances by one step on each cycle for maximum
throughput. Instructions can be decoded in one pipeline stage.
1. Registers- RISC machines have a large general-purpose register set.
Any register can contain either data or an address.
• Registers act as the fast local memory store for all data processing
operations.
• In contrast, CISC processors have dedicated registers for specific
purposes.
1. Load-store architecture—The processor operates on data held in
registers.
• Separate load and store instructions transfer data between the
register bank and external memory.
 The ARM Design Philosophy
Physical features that have driven the ARM processor design

• First, portable embedded systems require some form of battery power.

• The ARM processor has been specifically designed to be small to reduce power
consumption and extend battery operation—essential for applications such as
mobile phones and personal digital assistants (PDAs).
• High code density is another major requirement since embedded systems have
limited memory due to cost and/or physical size restrictions.
• High code density is useful for applications that have limited on-board
memory, such as mobile phones and mass storage devices.

• less space an instruction takes and the more work per instruction that a
microprocessor can do, the more dense its code is.
 The ARM Design Philosophy contd..

• In addition, embedded systems are price sensitive and use slow and
low-cost memory devices.
• For high-volume applications like digital cameras, every cent has to be
accounted for in the design.
• The ability to use low-cost memory devices produces substantial
savings.
• Another important requirement is to reduce the area of the die taken
up by the embedded processor.
• For a single-chip solution, the smaller the area used by the embedded
processor, the more available space for specialized peripherals.
• This in turn reduces the cost of the design and manufacturing since
fewer discrete chips are required for the end product.
 The ARM Design Philosophy contd..

• ARM has incorporated hardware debug technology within the

processor so that software engineers can view what is happening
while the processor is executing code.

• With greater visibility, software engineers can resolve issues faster,

which has a direct effect on the time to market and reduces overall
development costs.
 RISC and ARM

RISC Design Philosophy ARM Design Philosophy

•Instructions •Power efficiency
•Pipeline •High code density
•Registers •Memory footprint/ Die area
•Load/Store architecture •Debug technology
 ARM core Dataflow model
Arrows represent the flow of data, the
lines represent the buses, and the Data enters the processor core
boxes represent either an operation
unit or a storage area
through the Data bus.
The data may be an instruction to
execute or a data item
Von Neumann implementation of
the ARM— data items and
instructions share the same bus.
In contrast, Harvard
implementations of the ARM use
two different buses.
The instruction decoder
translates instructions before
they are executed.
 ARM core Dataflow model contd..

• Uses a load-store architecture-Load and store instructions

• There are no data processing instructions that directly manipulate data in
memory.
• Data processing is carried out in registers.
• Data items are placed in the register file—a storage bank made up of 32-bit
registers.
• Since the ARM core is a 32-bit processor, most instructions treat the registers
as holding signed or unsigned 32-bit values. The sign extend hardware
converts signed 8-bit and 16-bit numbers to 32-bit values as they are read
from memory and placed in a register.
 ARM core Dataflow model contd..
• ARM instructions typically have two source registers, Rn and Rm, and a single result or
destination register, Rd.
• Source operands are read from the register file using the internal buses A and B,
respectively.
• The ALU (arithmetic logic unit) or MAC (multiply-accumulate unit) takes the register
values Rn and Rm from the A and B buses and computes a result.
• Data processing instructions write the result in Rd directly to the register file.
• Load and store instructions use the ALU to generate an address to be held in the address
register and broadcast on the Address bus.
• One important feature of the ARM is that register Rm alternatively can be preprocessed
in the barrel shifter before it enters the ALU.
• Together the barrel shifter and ALU can calculate a wide range of expressions and
addresses
 ARM core Dataflow model contd..

• After passing through the functional units, the result in Rd is written

back to the register file using the Result bus.
• For load and store instructions the incrementer updates the address
register before the core reads or writes the next register value from or
to the next sequential memory location.
• The processor continues executing instructions until an exception or
interrupt changes the normal execution flow.