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CH 7

The document discusses memory and I/O interfacing with microprocessors. It describes how memory must be interfaced to allow the microprocessor to read instructions and data from memory by connecting address lines and control signals. I/O devices like keyboards are also interfaced using latches and buffers. A diagram shows how memory chips and I/O devices connect to a microprocessor via data lines, address lines, and control signals. Common memory devices like ROM, RAM and how they are organized are also covered.

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29 views20 pages

CH 7

The document discusses memory and I/O interfacing with microprocessors. It describes how memory must be interfaced to allow the microprocessor to read instructions and data from memory by connecting address lines and control signals. I/O devices like keyboards are also interfaced using latches and buffers. A diagram shows how memory chips and I/O devices connect to a microprocessor via data lines, address lines, and control signals. Common memory devices like ROM, RAM and how they are organized are also covered.

Uploaded by

Gcross NG
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Memory and I/O Interfacing

(Chapter 7)
Introduction
 Interface is the path for communication between two components.
Interfacing are two types, memory interfacing and I/O interfacing.
Memory Interfacing
When we are executing any instruction, we need the microprocessor
to access the memory for reading instruction codes and the data
stored in the memory. For this, both the memory and the
microprocessor requires some signals to read from and write to
registers.

The interfacing process includes some key factors to match with the
memory requirements and microprocessor signals.
The interfacing circuit therefore should be designed in such a way
that it matches the memory signal requirements with the signals of the
microprocessor.
Cont.
I/O Interfacing
 There are various communication devices like the keyboard, mouse,
printer, etc.

 So, we need to interface the keyboard and other devices with the
microprocessor by using latches and buffers.

 This type of interfacing is known as I/O interfacing.


Con.
The following figure shows a schematic diagram to interface memory chips
and I/O devices to a microprocessor.
Memory and I/O Interfacing
In memory interfacing:
 8 bit data line, 16 bit address line , control signals are
connected to corresponding lines of memory IC.
In I/O device interfacing:
 8 bit data line, only 8 bit address line , control signals are
connected to corresponding lines of I/O devices.
Cont.
Memory Devices
 Simple or complex, every microprocessor based system has
a Memory system.
 Almost all systems contain four common types of memory:
 Read only memory (ROM)
 Flash memory (EEPROM)
 Static Random access memory (SARAM)
 Dynamic Random access memory (DRAM).
 Before attempting to interface memory to the
microprocessor, it is essential to understand the operation of
memory components.
Memory Devices
 A general form diagram of ROM and RAM show in figure below.
Pin connections common to all memory devices are:
 Address connections: All memory devices have address inputs that
select a memory location within the memory device. Address inputs
are labelled (A0–An)
 Data connections: All memory devices have a set of data outputs
or input/outputs. Today many of them have bi-directional common
I/O pins.
Memory Devices
 Selection connections: Each memory device
has an input that selects or enables the memory
device. This kind of input is most often called a
chip select (CS) , chip enable (CE) or simply
select (S) input
 Control connections: The control input most
often found on the ROM is the output enable
(OE) or gate (G) this allows data to flow out of
the output data pins of the ROM.
Minimum mode Memory and I/O Interfacing

Block Diagram of Minimum mode Memory and I/O Interfacing in 8086 microprocessor
Minimum mode Memory and I/O Interfacing

 Address bus & Data bus are multiplexed on same lines


(AD0 to AD15).
 During first clock cycle, it serves as a memory/ IO
address bus.
 For second and third clock cycles it acts as data bus and
carries data.
 DE multiplexing refers to separating Address & Data
signals for read operations.
8086 Memory Organization
 The memory address space of the 8086-based
microcomputers has different logical and physical
organizations.
 Logically, memory is implemented as a single 1M × 8
memory bank. The byte-wide storage locations are
assigned consecutive addresses over the range from
00000H through FFFF
 Physically, memory is implemented as two in independent
512 Kbyte banks: the Low (even) bank and the high (odd)
bank.
(a) Logical memory organization, and (b) Physical memory
organization (high and low memory banks) of the 8086 microprocessor.
Cont.
 To distinguish between odd and even bytes, the CPU
provides a signal called BHE (bus high enable).
 BHE and A0 are used to select the odd and even byte,
as shown in the table below
Memory expansion
 In many applications, the microcomputer system
requirement for memory is greater than what is
available in a single device.
 There are two basic reasons for expanding memory
capacity:
1. The byte-wide length is not large enough
2. The total storage capacity is not enough bytes.
 Both these expansion needs can be satisfied by
interconnecting a number of IC.
Interfacing I/O Devices
Using I/O devices data can be transferred between the microprocessor
and the outside world.
This can be done in groups of 8 bits using the entire data bus. This is
called parallel I/O.
The other method is serial I/O where one bit is transferred at a time using
the SID and SOD pins on the Microprocessor.
8088/8086 architecture implements independent memory and
input/output address spaces
Memory address space- 1,048,576 bytes long (1M-byte):
00000HFFFFFH
Input/output address space- 65,536 bytes long (64K-bytes):0000HFFFFH
Interfacing I/O Devices
I/O devices can be interfaced in two ways
 Isolated mapped I/O

Memory mapped I/O


Isolated input/output
 It treats them separately from memory.
 I/O devices are assigned a “port number” with in
the 8-bit address range of 00H to FFH.
 The user in this case would access these devices
using the IN and OUT instructions only.
Memory-mapped Input/output
 It considers them like any other memory location.
 They are assigned a 16-bit address within the address
range of the 8086.
 The exchange of data with these devices follows the
transfer of data with memory. The user uses the same
instructions used for memory.
Cont.
The End

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