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CORTEX

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30 views16 pages

CORTEX

cortex topic mpmc jntuh eee and ece

Uploaded by

Marupaka
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Architecture profiles of ARM :

A, R and M and Secure Core series


WHAT IS CORTEX
• Every computer has a processor, whether it’s a small efficiency processor or a large performance
powerhouse, or else it wouldn’t be able to function. Of course, the processor, also called the CPU or
Central Processing Unit, is an important part of a functioning system, but it isn’t the only one.
• Today’s processors are almost all at least dual-core, meaning that the entire processor itself contains
two separate cores with which it can process information. But what are processor cores, and what
exactly do they do?
• A processor core is a processing unit which reads in instructions to perform specific actions.
Instructions are chained together so that, when run in real time, they make up your computer
experience. Literally everything you do on your computer has to be processed by your processor.
Whenever you open a folder, that requires your processor. When you type into a word document, that
also requires your processor. Things like drawing the desktop environment, the windows, and game
graphics are the job of your graphics card — which contains hundreds of processors to quickly work on
data simultaneously — but to some extent they still require your processor as well.
WHAT IS CORTEX
• The ARM Cortex is a family of microprocessors presented in
2005 by ARM Holdings and based on the ARMv7 instruction
set .

• The Cortex family is made up of a series of functional blocks


that can be connected to each other in order to meet
customer needs, so a specific Cortex processor does not
necessarily have all the functional units of the family.

• Cortex processors are available in single core or multicore


configurations and for each family there are multiple cores
with different performance.
Compared to version 6, the Cortex (VERSION 7) family introduces the
following innovations:

• The NEON unit developed to perform SIMD (Single Instruction stream,


Multiple Data stream ) operations on 64 or 128 bit vectors. The unit is
equipped with dedicated registers and the vectors can contain either 16
or 32 bit integers or 32-bit single-precision floating point numbers. The
unit operates in parallel to the main pipeline, the main pipeline
intervenes only when loading the instructions to be executed.
• The floating point unit VFPv3 doubles the registers of the previous
version, bringing them to 32 and introduces some new operations.

• The Thumb-EE instruction set is a derivative of the Thumb-2 instruction


set and was created to replace the Jazelle instructions. These instructions
are used to speed up the execution of code executed by virtual machines
like the one required by the Java language .
• TrustZone is a safe execution mode created to allow the execution of
secure code or to execute digital rights management (DRM) mechanisms.
There are FOUR architecture profiles: A, R and M

• A-Profile (Applications) is used in complex compute application areas, such as


servers, mobile phones and automotive head units. The Architecture (‘A’) profile
targets high performance markets such as mobile and enterprise.

• R-Profile (Real-Time) is used where real-time response is required. For example,


safety critical applications or those needing a deterministic response, such as
medical equipment or vehicle steering, braking and signaling. The Real-Time (‘R’)
profile provides high-performing processors for safety-critical environments.

• M-Profile (Microcontroller) is used where energy efficiency, power consumption


and size are important. M-Profile is especially suitable for deeply-embedded chips.
Recently, simple IoT devices have become a key application of M-Profile CPUs. For
example, in small sensors, communication modules and smart home products. The
Arm architecture is supported by built-in debug and visibility tooling.

• The SecureCore series derived from the M series and used for security
applications, such as Smart cards .
• The Cortex A family has been developed in order to achieve high
performance and reduced consumption.
• The processors of this series are divided into three cores,

– the core 5, 8 and 9. Core 5 has an 8-stage pipeline , the core 8 has two
13-stage pipelines and the core 9 has two 8-stage pipelines.
• The pipelines of the first ARMs were 3-stage and later units of up to 9
stages were developed.
• The development of a 13-stage processor was necessary to increase the
operating frequency of the processor.
• In core 8 the first instruction is loaded from the first pipeline,
the second instruction is loaded from the second pipeline; in the
case of constraints the constrained instruction is blocked until
the other instruction is completed and then the constraint is
resolved.
• Pipelines are independent and equivalent, except for the
multiplication operation that can only be performed from the
first pipeline. This is normally not a serious constraint since the
multiplication operations are normally rare.
• Core 9 constrained instructions to execute them in parallel,
providing better performance than core 8.
• Core 9 also manages the renaming of registers in order to
reduce constraints and improve execution parallel to the
instructions. The cores 5 and 9 can be assembled in integrated
that can contain up to 4 cores.
Key architectural points of ARM Cortex-A series processors
• A number of key points are common to the Cortex-A family of devices:
• 32-bit RISC core, with 16 × 32-bit visible registers with mode-based register banking.
• Modified Harvard Architecture (separate, concurrent access to instructions and data).
• Load/Store Architecture.
• Thumb-2 technology as standard.
• VFP and NEON options.
• Backward compatibility with code from previous ARM processors.
• 4GB of virtual address space and a minimum of 4GB of physical address space.
• Hardware translation table walking for virtual to physical address translation.
• Virtual page sizes of 4KB, 64KB, 1MB and 16MB. Cacheability attributes and access
permissions can be set on a per-page basis.
• Big-endian and little-endian data access support.
• Unaligned access support for basic load/store instructions.
• Symmetric Multi-processing (SMP) support on MPCore™ variants, that is, multi-core
versions of the Cortex-A series processors, with full data coherency at the L1 cache
level. Automatic cache and Translation Lookaside Buffer (TLB) maintenance
propagation provides high efficiency SMP operation
Architecture of A Series
The Cortex-A5 processor has the following features

• Full application compatibility with other Cortex-A series processors.

• Multiprocessing capability for scalable, energy efficient performance.

• Optional Floating-point or NEON units for media and signal processing.

• High-performance memory system including caches and memory

management unit.

• High value migration path from older ARM processors


Cortex-M35P
A tamper-resistant Cortex-M processor with optional software isolation using
TrustZone for Armv8-M.
Microprocessor-based system on a chip

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