Marathwada Mitramandal’s

COLLEGE OF ENGINEERING
Karvenagar, Pune
Accredited with ‘A’ Grade by NAAC

Presentation
On
Topic: HDL Design
Unit I: HDL

Subject: VLSI D&T

by

Mrs.H. N. Burande
Department of Electronics & Telecommunication Engineering

1
 Unit-1: Design with HDL

Session-1/38

Data types and data objects,entity and

architecture,Attributes

1) A VHDL Primer by J. Bhaskar

2) Charles H. Roth, Digital systems design using VHDL,
PWS.
Session Plan
Outline:
A. Attendance
B. Review of the previous session
C. Learning Outcomes of the session
D. Content
E. Student’s evaluation
F. Preparation for next session
G. Wrap up
B. Review of previous session:

● A quick recap of CO, PO, PSO

C. Learning Outcomes of the session:

● After completing this lecture students will be able to discuss

importance of HDL and to explore Hardware Description Language
(HDL) and respective digital design methodologies.
D. Content:
Content Learning / Faculty Typical Student Skill/
Methodology Approach Activity Competency
Developed
VLSI Design flow What is VLSI
design flow, why
it is important
Introduction to HDL -VHDL Awareness about
capabilities, advantages & Explains/ language
Discussion/
applications Questions/ capabilities and its
Listen/
Recap/ applications
Comprehends/
Facilitates/
VHDL basics- Design units and Participates/ Understanding of
Chalk and Board//PPT Guides/
libraries Answers/ language
Group Discussion Monitors/
Analyzes/ constructs
/Quiz/ Conducts/
Remembers/
Observes/
VLSI entity and architecture Understands/ How to write code
Organizes
concept Writes/Gives for given design
Explanation and
Ideas using VHDL
discussion
Entity and architecture Practising with
declaration with examples Examples for
better
understanding
 Unit-I

HDL Design
Reference Books:

1) A VHDL Primer by J. Bhaskar

2) Charles H. Roth, Digital systems design using
VHDL, PWS.
Learning Objectives of topic:
● Explanation of VLSI Design flow in detail with practical
aspects
● Importance of Hardware Description language (HDL) and
why and where it is applicable
Learning Outcomes of the session:

● After completing this lecture students will be able to discuss

importance of HDL and to explore Hardware Description
Language (HDL) and respective digital design methodologies.
Introduction to VHDL
 VHDL

Very Hard Difficult Language

 VHDL

VHSIC Hardware
Description Language
--------------------------------------

VHSIC --
Very High Speed Integrated Circuits
 A Brief History Of VHDL

• Funded by the US Department of Defense in the

80's.Originally meant for design
standardisation, documentation, simulation
and ease of maintenance.
Established as IEEE standard IEEE 1076 in
1987. An updated standard, IEEE 1164 was
adopted in 1993. In 1996 IEEE 1076.3
became a VHDL synthesis standard.
• Today VHDL is widely used across the
industry for design description, simulation
and synthesis.
 Modeling Digital Systems
• VHDL is for coding models of a digital system...

• Goal
– most ‘reliable’ design process, with minimum cost and
time
– avoid design errors!
 Basic VHDL Concepts
• Interfaces -- i.e. ports
• Behavior
• Structure
• Test Benches
• Analysis, simulation
• Synthesis
 VHDL CAPABILITIES
• VHDL is a programming language that allows one
to model and develop complex digital systems in
a dynamic environment.

• Allows you to designate in/out ports (bits) and

specify behavior or response of the system.

• Supports various techniques

e.g. FSM Descriptions, Boolean equations etc.
 Hardware Description Language
• HDL is any language(computer languages,
specification languages or modeling languages)
used for formal description and design of
electronic circuits( usually digital logic).
• It can describe,
➢ the circuit operation
➢Its design and organization
➢Tests to verify its operation by means of simulation
 HDL and Programming languages

HDL Programming Languages

• HDL is a “concurrent • Many programming
programming language” languages are inherently
which model multiple procedural, with limited
parallel processes(such as syntactical and schematic
f/fs, adders etc) that execute support to handle
independently of one concurrency.
another. For that reason,
VHDL is usually referred to
as a code rather than a
program.
• ‘Compiler’ refers to • A s/w compiler
synthesis, a process of converts the source-
transforming the HDL code listing into a
code listing into a microprocessor
physically realizable specific object-code,
gate netlist. for execution on the
target microprocessor.
• Pure HDLs are • General-purpose
unsuitable for general programming
purpose s/w languages are
application undesirable for
development. modeling hardware.
 Advantages of VHDL
• It allows behavior of the required system to
be described (modeled) and
verified(simulated) before synthesis tools
translate the design into real h/w (gates and
wires).
• VHDL allows the description of a
concurrent system.
• VHDL project is multipurpose. Being
created once, a calculation block can be
used in many other projects.
• VHDL project is portable(technology or
vendor independent language).
 Notes on the language syntax
• The language is not case sensitive.
• Comments are specified by preceding the
text with two consecutive dashes(--).
• Signal names and other VHDL identifiers
may contain letters, numbers and the
underscore character( _ ) (A-Z, a-z, _)
• An identifier must start with letter and
cannot end with underscore
e.g. c123 and ac_123 are legal.
2cd, abc_ are illegal.
 Notes on the language syntax
• Every VHDL statement must be terminated with
semicolon.
• Adjacent underscores are not allowed
 Library
• It is a collection of compiled VHDL units
• It enables sharing of compiled designs and
hides the source code from the users
• Commonly used functions, procedures and
user data types can be compiled into a user
defined library for use with all designs
• Library should be declared before each
entity declaration even if it is in the same
VHDL file
• To declare a library (i.e. to make it visible to
the design) two lines of code are needed ,
• one containing name of the library, the
other a use clause
A library structure can be as follows:
 Library syntax
LIBRARY library_name ;
USE library_name.package_name.package_parts ;
e.g.
LIBRARY IEEE ;
USE IEEE.std_logic_1164.all ;
LIBRARY work;
USE work.all ;
 Design Units and Libraries
• VHDL is defined such that more complex pieces are
built from simpler pieces

Librarie
s
Design Units

Statements

Expressions

Objects

Types
 Design Units and Libraries (cont.)
• VHDL model part that can be independently
analyzed (error checked) is a design unit
– Primary Design Units
• Entity Declaration
• Package Declaration
• Configuration Declaration
– Secondary Design Units
• Architectural Body
• Package Body
– Primary units analyzed before secondary units
 Design Units and Libraries (cont.)
• Two predefined libraries in VHDL
– STD - contains predefined VHDL constructs such as
types, objects, etc.
– WORK - the working library
• Many other libraries may exist as part of
development environment
– IEEE library - standard types and operators needed for
simulation and implementation
– User-defined libraries - designs for reuse
– Implementation specific libraries - logic families
 VHDL design units
1. Entity Description: It describes external
(interface) view of design.
2. Architecture Body : It consists of internal
description of design.
3. Configuration Description : It specifies the
binding of one architecture body from the many
architecture bodies associated with entity.
4. Package Declaration: It declares type, subtype,
subprogram etc.
5. Package Body: It contains definitions of
subprograms declared in package declaration.
 Entity
• It is the design’s interface to the external
circuitry
• Equivalent to pinout /package of an IC
• VHDL design must include one and only
one entity per module
• It can be used as a component in other
entities after being compiled into a library
 Entity syntax
entity entity_name is
port ( port_name : signal_mode signal_type ;
port_name : signal_mode signal_type ;
port_name : signal_mode signal_type );
end entity_name ;
 Port Definition
• Port declarations are identified by the keyword
‘port’
– Define design entity input/output signals
– Declaration must specify:
• The name (identifier)
• The direction, defined by keywords in, out,
inout, buffer
The information type; predefined types are
available
– BIT is predefined Boolean type with
values of 0 & 1
– INTEGER is a signed type
 Port Definitions (cont.)
• The port statement has the form of
PORT ( signal definition clause(s) );
– where the I/O signal definitions are
enclosed by parenthesis and followed by
a semicolon
– Multiple signal definitions are allowed
• Definitions are separated by a
semicolon
• There is no semicolon after the last
definition
 Modes

• Ports in the portlist have modes which

indicate the driver direction
• Mode also indicates whether or not the port
can be read from within the entity
– Four modes are available:
– Mode IN
– Mode OUT
– Mode INOUT
– Mode BUFFER
 Modeling Interfaces
• Entity declaration
– describes the input/output ports of a module

entity port port mode

name names (direction)
entity reg4 is
port ( d0, d1, d2, d3, en, clk : in
bit; punctuatio
q0, q1, q2, q3 : out bit ); n
end entity reg4;
reserved port
words type
 Entity Declaration

Entity

Architecture1 Architecture2 Architecture3

 Architecture Body

• It specifies the internal details of

an entity.

• It can be specified by three

modeling styles.
 Modeling styles in VHDL

• Dataflow
• Behavioral
• Structural
• Mixed
 Modeling the Dataflow way

• It consists of concurrent signal

assignment statements.
 Modeling the Dataflow way

• uses statements that defines the actual flow of data.

such as,
x <= y -- this is NOT less than equal to
this assigns the boolean signal y to the
value of boolean signal x... i.e. x = y

this will occur whenever ‘y’ changes..

• It consists of concurrent signal

assignment statements.
library ieee;
use ieee.std_logic_1164.all;
entity fulladd is
port(A,B,Cin: IN std_logic;
Sum, Cout: OUT std_logic);
end fulladd;
Architecture arch of fulladd is
Begin
Sum <= Cin XOR A XOR B;
Cout <= (A AND B) OR (Cin AND (A XOR B));
end a;
 Modeling the Behavior way

• It has a set of statements that are

executed sequentially.
 Modeling the Behavior way
• Architecture body
– describes an implementation of an entity
– may be several per entity
• Behavioral architecture
– describes the algorithm performed by the
module
– Contains -> process statements, each
containing sequential statements, including
• signal assignment statements and
• wait statements
 The Behavior way EX.1

entity reg4 is
port ( d0, d1, d2 : in bit
d3, en, clk : in bit;
q0, q1, q2, q3 : out bit );
end reg4;

architecture behav of reg4 is

begin
process (d0, ... )
...
begin
...
end process ;
end behav;
 The Behavior way – EX. 2
architecture behav of reg4 is
begin
process (d0, d1, d2, d3, en, clk) sensitivity
variable stored_d0, stored_d1, stored_d2,list stored_d3 : bit;
begin
if en = '1' and clk = '1' then
stored_d0 := d0; notice := syntax
stored_d1 := d1; used for equating values
stored_d2 := d2; from signals...
stored_d3 := d3;
end if;
q0 <= stored_d0 after 5 ns; simulates real-world
q1 <= stored_d1 after 5 ns; propagation delays.
q2 <= stored_d2 after 5 ns;
q3 <= stored_d3 after 5 ns;
end process;
end behav;
 Modeling the Structural way

• Structural architecture
– implements the module as a
composition of subsystems
– contains
• signal declarations, for internal
interconnections
– the entity ports are also treated as signals
• component instances
– instances of previously declared
entity/architecture pairs
• port maps in component instances
– connect signals to component ports
Structural way -- EX.1
 Structural way cont..
• First declare D-latch & and-gate entities and architectures

notice semicolon placements -- odd as it is, omit from last statement

entity d_latch is entity and2 is
port ( d, clk : in bit; port ( a, b : in bit;
q : out bit ); y : out bit );
end entity d_latch; end entity and2;

architecture basic of d_latch is architecture basic of and2 is

begin begin
process (clk, d) process (a, b)
begin begin
if clk = ‘1’ then y <= a and b ;
q <= d ; end process ;
end if; end basic;
end process;
end basic;
 Structural way...
• Declare corresponding components in register
architecture body

architecture struct of reg4 is

component d_latch
port ( d, clk : in bit; q : out bit
);
end component;
component and2
port ( a, b : in bit; y : out bit );
end component;
signal int_clk : bit;
...
 Structural way..
• Now use them to implement the register

...
begin
bit0 : d_latch port map ( d0, int_clk,
q0 );
bit1 : d_latch port map ( d1, int_clk,
q1 );
bit2 : d_latch port map ( d2, int_clk,
q2 );
bit3 : d_latch port map ( d3, int_clk,
q3 );
gate : and2 port map ( en, clk, int_clk );
end struct;
• Component instantiation is a
concurrent statements. Therefore the
order of statement is not important.
• The architecture body is composed of
two parts:
1.The declarative part i.e. before the
keyword ‘begin’.
2.The statement part i.e. after the
keyword ‘begin’.
 Mixed Behavior and Structure
• An architecture can contain both behavioral and
structural parts
– process statements and component instances
• collectively called concurrent statements
– processes can read and assign to signals
• Example: register-transfer-level (RTL) Model
– data path described structurally
– control section described behaviorally
Mixed Example
 Mixed Example
entity multiplier is
port ( clk, reset : in bit;
multiplicand, multiplier : in integer;
product : out integer );
end multiplier;

architecture mixed of mulitplier is

signal partial_product, full_product : integer;
signal arith_control, result_en, mult_bit, mult_load : bit;
begin
arith_unit : entity work.shift_adder(behavior)
port map ( addend => multiplicand, augend =>
full_product,
sum => partial_product,
add_control => arith_control );
result : entity work.reg(behavior)
port map ( d => partial_product, q => full_product,
en => result_en, reset => reset );
...
 Mixed Example
…
multiplier_sr : entity work.shift_reg(behavior)
port map ( d => multiplier, q => mult_bit,
load => mult_load, clk => clk );
product <= full_product;
process (clk, reset)
-- variable declarations for control_section
-- …
begin
-- sequential statements to assign values to control
signals
-- …
end process;
end mixed;
Student’s evaluation

VHDL Syntax
Is VHDL Case sensitive?
Is VHDL Concurrent/Sequential language?
Assignment for next session

Write entity and architecture for Full adder

 Wrap up

VHDL Long form

VHDL Constructs
Library
Entity
Architecture