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Introduction To Verilog

Verilog is a hardware description language used to describe low-level digital circuits. It has several levels of abstraction, from switch level up to behavioral level. A Verilog module defines inputs, outputs, and the overall behavior of the design using constructs like initial and always blocks. Data types in Verilog include wires for signals, regs for values that change over time, and parameters for configurable constants.

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France Mae Camogao
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22 views

Introduction To Verilog

Verilog is a hardware description language used to describe low-level digital circuits. It has several levels of abstraction, from switch level up to behavioral level. A Verilog module defines inputs, outputs, and the overall behavior of the design using constructs like initial and always blocks. Data types in Verilog include wires for signals, regs for values that change over time, and parameters for configurable constants.

Uploaded by

France Mae Camogao
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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INTRODUCTION TO

VERILOG
PREPARED BY: ENGR. FRANCE MAE D. CAMOGAO
VERILOG

• Is a Hardware Descriptive Language (HDL) standardized as IEEE 1364-2001


• Verilog is used to describe low-level hardware
• Syntax is similar to the C-Language
VHDL

• VHDL stands for VHSIC (very high speed integrated circuit) Hardware
Descriptive Language
• It can model the behavior and structure of digital system at multiple
abstraction levels
• VHDL is strongly typed and very deterministic
VERILOG MODULE
VERILOG MODULE:

MODULE - THIS KEYWORD INDICATES THE BEGINNING OF A VERILOG MODULE


DEFINITION.
VERILOG MODULE:

MODULE NAME - THIS IS THE NAME GIVEN TO THE MODULE. IT SHOULD BE A USER-DEFINED NAME THAT
REFLECTS THE PURPOSE OF THE MODULE.
VERILOG MODULE:

INPUT WIRE INPUT_SIGNAL 1- THIS LINE DECLARES AN INPUT SIGNAL NAMED “INPUT_SIGNAL1" WITH THE
“WIRE” DATA TYPE. THE “INPUT” KEYWORD SIGNIFIES THAT THIS SIGNAL IS AN INPUT TO THE MODULE.
VERILOG MODULE:

OUTPUT WIRE OUTPUT_SIGNAL 1- THIS LINE DECLARES AN OUTPUT SIGNAL NAMED OUTPUT_SIGNAL WITH THE
WIRE DATA TYPE. THE OUTPUT KEYWORD INDICATES THAT THIS SIGNAL IS AN OUTPUT OF THE MODULE.
VERILOG DATA
TYPES
VERILOG DATA TYPES:
• Wire: A wire is a continuous signal that can be used to connect different logic
elements. It's typically used to model connections between different gates or
modules.
• Reg: Despite its name, a "reg" in Verilog can represent both sequential and
combinational logic. It's used to represent values that can change over time. It's
often used for modeling sequential elements like registers and flip-flops.
• Integer: The integer data type is used to represent whole numbers. It's a basic
numeric type that can be used for various purposes like counting or indexing.
• Real: The real data type is used to represent floating-point numbers. It's often used
for modeling analog signals or for performing floating-point computations.
• Time: The time data type is used to represent time values. It's often used for
modeling delays or timing constraints within a circuit.
VERILOG DATA TYPES:
• Parameter: Parameters are used to define constants or values that can be easily changed
at the module level. They are typically used for configuring various aspects of a design.
• Net: A net is a more general term that encompasses both wires and other types of
connections between elements. It's a broader concept that covers the interconnection of
different signals.
• Bit: A single bit data type represents a binary value, either 0 or 1. It's the smallest unit of
information in digital design.
• Bit Vector: A bit vector is a collection of multiple bits that can be used to represent
binary values of various sizes. It's often used for representing multi-bit signals or data
buses.
• Logic: The logic data type represents multi-bit values where each bit can take on the
values '0', '1', 'x' (unknown), 'z' (high-impedance), or 'b' (binary).
VERILOG (LEVEL OF ABSTRACTIONS)
• SWITCH LEVEL
• GATE LEVEL
• DATA FLOW LEVEL
• BEHAVIORAL LEVEL
SWITCH LEVEL

• At this level a module can be implemented in terms of switches


• Here nmos and pmos are used as switches for the design
SWITCH LEVEL
GATE LEVEL

• At this level a module is implemented in terms of logic gates


• Gate level is the lowest level of abstraction
• Basic logic gates are available as predefined primitives
GATE LEVEL
DATA FLOW LEVEL

• Register transfer level


• At this level, module is designed by specifying the data flow
• Signals are assigned by the data manipulating equations
• Design is implemented using continuous assignments
• All such assignments are concurrent in nature
DATA FLOW LEVEL
BEHAVIORAL LEVEL

• This is the highest level of abstraction provided by HDL


• Behavioral level describes the system by its behavior
• Different elements like function, task, and block can be used
• Two important constructs under this level are initial and always
BEHAVIORAL LEVEL

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