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Lecture 5 (ImplementationOfAlgebraicFunctions)

This lecture covers implementing algebraic functions using logic gates. It discusses implementing switching functions using AND and OR gates, as well as simplified switching functions. It also discusses implementing POS expressions and circuits that are not in SOP or POS form. The lecture describes integrated circuits and common logic gate ICs. It provides important tips on constructing gates and defines positive and negative logic.

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21 views

Lecture 5 (ImplementationOfAlgebraicFunctions)

This lecture covers implementing algebraic functions using logic gates. It discusses implementing switching functions using AND and OR gates, as well as simplified switching functions. It also discusses implementing POS expressions and circuits that are not in SOP or POS form. The lecture describes integrated circuits and common logic gate ICs. It provides important tips on constructing gates and defines positive and negative logic.

Uploaded by

sd
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Lecture 5

Implementation of Algebraic Functions


In this lecture we will cover the following:
Implementing Switching Functions
Implementing Simplified Switching Functions
Today’s Implementing POS Expression
Topics Implementing Circuits that are neither in SOP
nor in POS
Integrated Circuits
Important Points
Positive Logic and Negative Logic

2
Implementing Switching
Functions
At first, we shall implement the switching functions using
AND, OR and NOT gates.
Consider the following function:

3
Implementing Switching
Functions (Contd…)
Each of the product terms is formed by an AND gate. In this example, all of
the AND gates have three inputs. The outputs of the AND gates are used as
inputs to an OR gate.
This is an example of a two-level circuit. The number of levels is the maximum
number of gates through which a signal must pass from the input to the
output.
In this example, all signals go first through an AND gate and then through an
OR gate.
When inputs are available both uncomplemented and complemented,
implementations of both SOP and POS expressions result in two-level circuits.

4
Implementing Simplified Switching
Function
We have already seen that one of
the simplified versions of the above
function with minimum SOP
expression is
f = x’y + xy’ + xz
The implementation of this
simplified function results in less
complex circuit which is as follows:

5
Implementing Simplified Switching Function (Contd...)
Implementing Simplified
Switching Function
If complemented inputs are not
available, then an inverter (a
NOT gate) is needed for each
input that is required to be
complemented (x and y in this
example).
The circuit of Figure 2.9 shows
the NOT gates that must be
added to the circuit of Figure
2.8 to implement the switching
function f.

6
Implementing POS
Expression
A POS expression (assuming all
inputs are available both
uncomplemented and
complemented) corresponds to
a two-level OR–AND network.
For example, the following POS
expression
f = (x + y)(x’ + y’ + z)

is implemented as follows:

7
Implementing Functions that are neither in SOP nor in
POS
• When we implement functions that are neither in SOP nor in
POS form, the resulting circuits are more than two levels.
• For example, consider the following function:

• This function is implemented (with 4-level circuit) as follows:

8
Implementing Functions that are neither in SOP nor in
POS
Consider another function that is neither in SOP nor in POS.

This function is implemented in 3-level circuit as follows:

9
Integrated Circuits
Gates are typically available in dual in-line pin packages (DIPs) of 14
connector pins.
These packages are often referred to as chips. (Larger packages of 16,
18, 22, and more pins are used for more complex logic.)
These packages contain Integrated Circuits (ICs). Integrated circuits
are categorized as small-scale integration (SSI) when they contain just
a few gates.
Medium Scale Integrated (MSI) circuits contain as many as 100 gates.
The terminology Large-Scale Integration (LSI), Very Large Scale
Integration (VLSI), and Giga-Scale Integration (GSI) is used for even
more complex packages, including complete computers.

10
Integrated Circuits (Contd..)
Two of the connector pins are used to provide power to the
chip. That leaves 12 pins for logic connections (on a 14-pin chip).
Thus, we can fit 4 two-input gates on a chip. (Each gate has two
input connections and one output connection. There are enough
pins for four such gates.)
Similarly, there are enough pins for 6 one-input gates (NOTs)
(which will make 6 pins for inputs and 6 pins for outputs and 2
pins for power)) , or 3 three-input gates (which will make 9 pins
for inputs and 3 pins for outputs and 2 pins for power), or 2 four-
input gates (which will make 8 pins for inputs, 2 pins for outputs,
2 pins for power with two pins unused).

11
Integrated Circuits (Contd..)
A list of the common AND, OR, and NOT integrated
circuits that might be encountered in the laboratory
is:
7404 6 (hex) NOT gates
7408 4 (quadruple) two-input AND gates
7411 3 (triple) three-input AND gates
7421 2 four-input (dual) AND gates
7432 4 (quadruple) two-input OR gates

12
Important Points
If a three-input OR (or AND) is needed, and only two-input ones are
available, it can be constructed as follows:

Also, if we need a two-input gate and there is a leftover three-input one


(because they come three to a package), we can connect the same signal to
two of the inputs (since a.a = a, and a + a = a).

13
Important Points (Contd...)

Also, we could connect a logic 1 (5 V) to one of the inputs of


an AND gate or a logic 0 (ground) to one of the inputs of an
OR gate, as:

14
Positive Logic and Negative Logic

In the laboratory, logic-0 and logic-1 are represented by two voltages: often
0 (ground) and 5 V.
Most commonly, the higher voltage is used to represent 1 and the lower
voltage to represent 0. This is referred to as positive logic.
The opposite choice is also possible, that is, use the higher voltage to
represent 0 and lower voltage to represent 1. That is referred to as negative
logic.
Consider the truth table of Table 2.9a, where the behavior of the gate is
described just in terms of high (H) and low (L).
The positive logic interpretation of Table 2.9b produces the truth table for
an OR gate.
The negative logic interpretation of Table 2.9c is that of an AND gate.

15
Positive Logic and Negative Logic (Contd...)

Hence, from the above tables, we can conclude that Positive Logic OR
gate is equal to Negative Logic AND gate.

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