EE204: Computer Architecture

Chapter 4

Section 4.4
Control
 Control unit takes input from
 the instruction opcode bits

 Control unit generates

 ALU control input
 write enable (possibly, read enable also) signals for each storage
element
 selector controls for each multiplexor
 ALU Control
 LW and SW use ALU for address calculation
 R-type instructions use ALU for any of the first 5 operations
depending on the funct field
 For branch equal, subtract is required
 ALU Control
2

ALUO 4
Main ALU To
p ALU
Control Control ALU
control
input
6
 ALU must perform Instruction ALUOp generation
 add for load/storesfunct field
(ALUOp 00)by main control
 sub for branches (ALUOp 01)
 one of and, or, add, sub, slt for R-type instructions, depending on the
instruction’s 6-bit funct field (ALUOp 10)
Setting up the ALU Control
 Designing the Main Control

 Observations about MIPS instruction format

 opcode is always in bits 31-26
 two registers to be read are always rs (bits 25-21) and rt (bits 20-16)
 base register for load/stores is always rs (bits 25-21)
 16-bit offset for branch equal and load/store is always bits 15-0
 destination register for loads is in bits 20-16 (rt) while for R-type
instructions it is in bits 15-11 (rd) (will require multiplexor to select)
 Datapath with Control I
PCSrc

1
Add M
u
x
4 ALU 0
Add result
New multiplexor RegWrite Shift
left 2

Instruction [25– 21] Read

Read register 1 Read MemWrite
PC data 1
address Instruction [20– 16] Read MemtoReg
ALUSrc
Instruction register 2 Zero
1 Read ALU ALU
[31– 0] Write data 2 1 Read
M result Address 1
u register M data
Instruction Instruction [15– 11] x u M
memory Write x u
0 data Registers x
0
Write Data 0
RegDst data memory
Instruction [15– 0] 16 Sign 32
extend ALU MemRead
control
Instruction [5– 0]

ALUOp

what are the functions of the control signals?

 Control Signals
Signal Name Effect when deasserted Effect when asserted

RegDst The register destination number for the The register destination number for the
Write register comes from the rt field (bits 20-16) Write register comes from the rd field (bits 15-11)
RegWrite None The register on the Write register input is written
with the value on the Write data input
AlLUSrc The second ALU operand comes from the The second ALU operand is the sign-extended,
second register file output (Read data 2) lower 16 bits of the instruction
PCSrc The PC is replaced by the output of the adder The PC is replaced by the output of the adder
that computes the value of PC + 4 that computes the branch target
MemRead None Data memory contents designated by the address
input are put on the first Read data output
MemWrite None Data memory contents designated by the address
input are replaced by the value of the Write data inpu
MemtoReg The value fed to the register Write data input The value fed to the register Write data input
comes from the ALU comes from the data memory

Effects of the seven control signals

 Datapath with Control
0
M
u
x
ALU
Add result 1
Add Shift PCSrc
RegDst left 2
4 Branch
MemRead
Instruction [31 26] MemtoReg
Control
ALUOp
MemWrite
ALUSrc
RegWrite

Instruction [25 21] Read

PC Read register 1
address Read
Instruction [20 16] data 1
Read
register 2 Zero
Instruction 0 Registers Read ALU ALU
[31– 0] 0 Read
M Write data 2 result Address 1
Instruction u register M data
u M
memory Instruction [15 11] x u
1 Write x Data
data x
1 memory 0
Write
data
16 32
Instruction [15 0] Sign
extend ALU
control

Instruction [5 0]

MIPS datapath with the control unit: input to control is the 6-bit instruction
opcode field, output is seven 1-bit signals and the 2-bit ALUOp signal
Datapath with Control
 PCSrc cannot be
0
set directly from the
M
u opcode: zero test
x
ALU
Add result 1
outcome is required
Add Shift PCSrc
RegDst left 2
4 Branch
MemRead
Instruction [31 26] MemtoReg
Control
ALUOp
MemWrite
ALUSrc
RegWrite

Instruction [25 21] Read

PC Read register 1
address Read
Instruction [20 16] data 1
Read
register 2 Zero
Instruction 0 Registers Read ALU ALU
[31– 0] 0 Read
M Write data 2 result Address 1
Instruction u register M data
u M
memory Instruction [15 11] x u
1 Write x Data
data x
1 memory 0
Write
data

Datapath with Instruction [15 0]

16
Sign
extend
32

ALU
control

Control II (cont.) Instruction [5 0]

Determining control signals for the MIPS datapath based on instruction opcode

Memto- Reg Mem Mem

Instruction RegDst ALUSrc Reg Write Read Write Branch ALUOp1 ALUp0
R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 X 0 0 0 1 0 1
R-type instruction (add)
I-type instruction (lw)
Implementing JUMPs