Lecture 4 Part 2: CPU and Memory

 Every instruction that is executed by the Central

Processing Unit (CPU) requires memory access
 Memory is actually separated both physically and
functionally from the CPU
 Primary memory holds program instructions and data
and interacts directly with the CPU during the program
execution
 It is equivalent to the mailboxes in the LMC model
 Secondary storage is used for long term storage and is
managed as Input/Output
 Program code and data are moved from secondary
storage to primary memory for CPU execution

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CPU: Major Components
 The CPU consists of ALU and CU as defined here:
 Arithmetic Logic Unit (ALU)
 It performs calculations and comparisons
 It corresponds directly to the calculator in the LMC
 Control Unit (CU) controls and interprets the execution of the
instructions
 It performs the fetch/execute cycle
 It accesses program instructions and issues commands to the

ALU
 It moves data to and from CPU registers and other hardware

components without changing the data

 IT corresponds to the Little Man in the LMC model

 Subcomponents:
 Memory management unit: supervises fetching instructions

and data from memory

 I/O Interface: sometimes combined with memory management

unit as Bus Interface Unit

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System Block Diagram

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The Little Man Computer

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Concept of Registers
 Registers are small, permanent storage
locations within the CPU used for a particular
purpose
 They are manipulated directly by the Control
Unit
 They are wired for specific functions
 Their size is in bits or bytes (not in MB like
memory)
 They can hold data, an address, or an
instruction
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Registers
 Use of Registers
 They act as a scratchpad for currently executing program
 They hold data needed quickly or frequently

 They store information about status of CPU and currently

executing program
 The address of the next program instruction

 Signals from external devices

 General Purpose Registers

 They are User-visible or program-visible registers
 They hold intermediate results or data values, e.g., loop
counters
 They are equivalent to LMC’s calculator
 Typically there are several dozen registers in current CPUs

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Special-Purpose Registers
 The Control Unit contains several important registers
 Program Counter Register (PC)
 It is also called an Instruction Pointer (IP)
 It contains the address of the next instruction to be
fetched
 Instruction Register (IR)
 It stores the actual instruction which is being
executed currently
 The LMC did not have this register; the Little Man
remembered the instruction; the brain served as IR
 Memory Address Register (MAR)
 Contains an address in memory which is to be read from or
written to.

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Special-Purpose Registers

 Memory Data Register (MDR)

 After a read, MDR contains the contents at the
address given in the MAR.
 Before a write, MDR contains whatever is to be
copied to the address in the MAR
 Status Registers
 They hold status of CPU and currently executing
program
 They hold Flags (one bit Boolean variable) to track
conditions like arithmetic carry and overflow, power
failure, internal computer error
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Register Operations
 Stores values from other locations (from
other registers and memory locations)
 Data from another location can be added
or subtracted from the value previously
stored in a register
 Shift or rotate data by one or more bits
 Test contents of the register for conditions
such as zero, positive or negative

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Operation of Memory
 Each memory location has a unique address
 Address from an instruction is copied to the
MAR, which finds the location in memory
 The CPU determines if it is a store or
retrieval
 Then the transfer takes place between the
MDR and the memory
 MDR is a two way register

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Relationship between MAR,
MDR and Memory
Address Data

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MAR-MDR Example

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Visual Analogy of Memory

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Fetch-Execute Cycle
 This is a two-cycle process because both instructions
and data are in memory
 Fetch Cycle
 This cycle decodes or finds instruction, loads
contents from memory into register and signals
ALU
 Execute Cycle
 This cycle performs operation that the instruction
requires
 The data is moved or transformed

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LMC vs CPU
Fetch and Execute Cycle

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Load Fetch/Execute Cycle
1. PC  MAR Transfer the address from the
PC to the MAR
2. MDR  IR Transfer the instruction to the
IR
3. IR[address]  MAR Address portion of the
instruction loaded in MAR
4. MDR  A Actual data copied into the
accumulator
5. PC + 1  PC Program Counter incremented

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Store Fetch/Execute Cycle
1. PC  MAR Transfer the address from the
PC to the MAR
2. MDR  IR Transfer the instruction to the
IR
3. IR[address]  MAR Address portion of the
instruction loaded in MAR
4. A  MDR* Accumulator copies data into
MDR
5. PC + 1  PC Program Counter incremented
*Notice how Step #4 differs for LOAD and STORE

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ADD Fetch/Execute Cycle
1. PC  MAR Transfer the address from the
PC to the MAR
2. MDR  IR Transfer the instruction to the
IR
3. IR[address]  MAR Address portion of the
instruction loaded in MAR
4. A + MDR  A Contents of MDR added to
contents of accumulator
5. PC + 1  PC Program Counter incremented

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LMC Fetch/Execute Cycle
SUBTRACT IN OUT HALT
PC  MAR PC  MAR PC  MAR PC  MAR
MDR  IR MDR  IR MDR  IR MDR  IR
IR[addr]  MAR IOR  A A  IOR
A – MDR  A PC + 1  PC PC + 1  PC
PC + 1  PC
BRANCH BRANCH on Condition
PC  MAR PC  MAR
MDR  IR MDR  IR
IR[addr]  PC If condition false: PC + 1  PC
If condition true: IR[addr]  PC

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 Example
Let us now consider a two-instruction program segment that loads a number from memory, and
adds a second number to it. We will assume the given contents in the four memory locations:
65, 66, 90 and 92
Program Counter (PC) : 65
Value in Mem location 65 : 590 (LOAD 90)
Value in Mem location 66 : 192 (ADD 92)
Value in Mem location 90 : 111
Value in Mem location 92 : 222
1st instruction Load 90
PC → MAR MAR now has 65
MDR → IR IR has instruction 590
--------------------------------- end of fetch
IR[address] → MAR MAR has 90, location of data
MDR → A Move 111 from MDR to A
PC + 1 → PC PC now points to 66
----------------------------------end of execution; first instruction

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 Example
 2nd Instruction ADD 92
PC → MAR MAR now contains 66
MDR → IR IR contains instruction 192
----------------------------end of fetch
IR[address] → MAR MAR now has 92
A + MDR → A 111 + 222 = 333 in A
PC + 1 = PC PC now points to 67
----------------------------- end of execution; second instruction

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