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12 Memory 3

1) Byte address 1200 maps to block 11 in a direct-mapped cache with 64 blocks of 16 bytes each. 2) In a 2-way set associative cache with 64 blocks of 16 bytes, byte address 1200 maps to set 11. 3) In a 64KB cache with 16 byte blocks and 32-bit addresses, the tag is 16 bits, index is 12 bits, and offset is 4 bits for direct-mapped. The tag is 18 bits, index is 10 bits, and offset is 4 bits for 4-way set associative. The tag size is variable and index is 0 bits for fully associative.

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60 views15 pages

12 Memory 3

1) Byte address 1200 maps to block 11 in a direct-mapped cache with 64 blocks of 16 bytes each. 2) In a 2-way set associative cache with 64 blocks of 16 bytes, byte address 1200 maps to set 11. 3) In a 64KB cache with 16 byte blocks and 32-bit addresses, the tag is 16 bits, index is 12 bits, and offset is 4 bits for direct-mapped. The tag is 18 bits, index is 10 bits, and offset is 4 bits for 4-way set associative. The tag size is variable and index is 0 bits for fully associative.

Uploaded by

max scalom
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Computer Systems Architecture

Cache Mapping
Problems
Problem 1

Consider a direct-mapped Cache with 64 blocks and a block size of


16 bytes. To what block number does byte address 1200 map?

3
Problem 1-- Solution
Step-1:
You have to find the block size first.
1 block = 16 bytes

Step-2:
Then find the memory block number that byte address 1200 belongs to.
Since 1 block is 16 bytes,
byte address 0 ~ 15 : block 0
16 ~ 31: block 1
32~ 47: block 2
…
Therefore,
floor (byte address / block size) = memory block # 4
Problem 1-- Solution
So floor( 1200/16) = 75.

Step 3:
Then you need to find which cache block memory block 75 maps to.
In a direct-mapped cache,
cache block # = memory block # mod (total block number of cache)
Therefore, 75 mod 64 = 11.

5
Problem 2

Consider a 2-way set associative cache with 64 blocks and a block


size of 16 bytes. To which set number does byte address 1200
map?

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Problem 2-- Solution

Step 1:
Since the cache is 2-way set associative, a set has 2 cache blocks. Because there
are 64 cache blocks, there are 32 sets in the cache (set 0 ~ set 31).

Step 2:
Byte address 1200 belongs to memory block 75.
Then
set # = memory block # mod (total sets in the cache).
Therefore, 75 mod 32 = 11.
So memory block 75 maps to set 11 in the cache (cache block 22 and 23) and
chooses one of them. How to choose one of them is a very long story.
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Problem 3

A 64KB cache has 16 byte blocks. If addresses are 32 bits, how


many bits are used the tag, index, and offset in this cache?

8
Problem 3-- SOLUTION
For Direct Mapped Cache

Number of bits for addressing word= 4bit


Number of cache lines = Size of cache / size of Block
64KB/16B = 4K = 12bits
Remaining 16 bits for tag so division of 32 bits is like

TAG GROUP OFFSET


16 bits 12 bits 4 bits

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Problem 3-- SOLUTION
For 4-way set associative Cache

Number of bits for addressing word= 4bit


Number of lines/blocks in each cache set is 4
so each cache set is 4*16B = 64B

Number of cache sets = size of cache/size of cache set


64KB/64B = 1K
TAG INDEX OFFSET
18 bits 10 bits 4 bits
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Problem 3-- SOLUTION
For Fully Associative Cache

Number of index bits = 0 because any block can be stored in any line

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Problem 4
Caches are important to providing a high-performance memory
hierarchy to processors. Below is a list of 32-bit memory address
reference, given as word addresses

21, 166, 201, 143, 61, 166, 62, 133, 111,143, 144, 61

 What will be the final cache contents for a Fully associative cache with one word
blocks and a total size of 6 blocks?
 Use LRU replacement. For each reference identify the index bits, the tag bits, the
block offset bits, and if it is a hit or a miss

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Problem 4-- SOLUTION
Caches are important to providing a high-performance memory hierarchy
to processors. Below is a list of 32-bit memory address reference, given
as word addresses
21, 166, 201, 143, 61, 166, 62, 133, 111,143, 144, 61

Cache index Address in Cache Hit/ Miss

0 21,62 MM

1 166,133 MM

2 201,111 MM

3 143 MH

4 61,144 MM

5 166,61 MM
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Problem 5
Caches are important to providing a high-performance memory hierarchy to processors.
Below is a list of 32-bit memory address reference, given as word addresses
21, 166, 201, 143, 61, 166, 62, 133, 111,143, 144, 61

 What will be the final cache contents for a Direct Mapped cache with two word
blocks and a total size of 24 blocks?

 Use LRU replacement. For each reference identify the index bits, the tag bits,
the block offset bits, and if it is a hit or a miss

14
Problem 5--SOLUTION

 What will be the final cache contents for a Direct Mapped cache with
two word blocks and a total size of 24 blocks?
21, 166, 201, 143, 61, 166, 62, 133, 111,143, 144, 61

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